A Novel Circuit Architecture for High Performance of High-order Subharmonic Mixers

A novel circuit architecture for high performance of high-order subharmonic (SH) mixers is proposed in this paper. According to the specified harmonic mixing order, one or more mixer diodes sub-arrays and corresponding power divider as well as phase shift network for RF and LO signals are arranged in the circuit. This proposed SH mixer circuit has improved conversion loss, wide dynamic range and high port isolation for high-order SH mixers. By phase cancellation of idle frequencies, the proposed SH mixer circuit can eliminate complicated design procedure of idle frequency circuits; by phase cancellation of leakage LO power to RF and IF port, and leakage RF power to LO port, the mixer circuit can get high port isolation in LO-IF/RF and RF-LO. The increased antiparallel diode pairs in each sub-array will also lead to well performance by lowering effective series resistance. The proposed SH mixer circuit can be easily realized with power divider and phase shift network for RF and LO signals.     

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.This research was supported by the National Science Foundation under grant MIP-9222481.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

Short Millimeter Low Local Wavelength Mixer with Oscillator Power

This paper discusses development, for the 240-GHz region, of whisker contacted diode mixers with LO powers between 10 and 50 µW. Mixer requirements for low parasitic diodes, situated in high-embedding impedance circuits are described and appropriate RF and IF circuit designs presented. A capacitive post RF matching circuit for a full-height waveguide is developed with superior bandwidth characteristics at high impedance levels and greater ease of fabrication than usual matching circuits in reduced height guide. Corroborating experimental results are presented for an X-band model and for a 235-GHz mixer.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies

The conventional practice for testing analog or RF integrated circuits is specification-based testing, which relies on the direct measurement of the circuit performance parameters. This approach offers good test quality but at the price of extremely high testing costs. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring them directly. In this paper, we perform efficiency evaluation of this strategy, and in particular we perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is evaluated in terms of model accuracy by using classical metrics such as average and maximal prediction errors, and in terms of prediction reliability by introducing a new metric called Failing Prediction Rate (FPR). Results are illustrated on two case studies for which we have experimental test data.     

模拟集成电路的测试与故障检测技术

本文综述了模拟集成电路的测试及故障检测等有关问题，首先介绍面向性能的测试方法，然后讨论故障模型和面向故障的测试方法，在介绍了模拟集成电路的可测性设计技术之后，讨论了利用电源监测进行故障检测的方法。     

RF and IF ports matching circuit synthesis for a simultaneousconjugate-matched mixer using quasi-linear analysis

A quasi-linear two-port approach between RF and IF ports to design a simultaneous conjugate-matched mixer is presented in this paper. Conventionally, mixer design is treated as a nonlinear three-port device problem. Nonetheless, with the exception of the large-signal local oscillator (LO) that exists at the LO port, the input RF and output IF signals that exist at the RF and IF ports, respectively, are small signals. Consequently, mixers can be approximated as bilateral quasi-linear two-port circuits with a time-variant transfer function between the RF and IF ports, in which the LO port of the mixer is treated as part of the two-port network. With this approximation, it can be shown mathematically that the optimum source and load matching networks required for attaining simultaneous conjugate match at the RF and IF ports are actually time invariant, thus implying that it is possible to synthesize these optimum impedance values. This proposed mixer design technique, together with the equations derived, are verified with block-diagram simulation and experimental measurements of two 2.4-GHz RF/420-MHz IF double-balanced diode mixers     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Monolithic SiGe Up‐/Down‐Conversion Mixers with Active Baluns

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on‐chip 1 to 6 GHz up‐conversion and 1 to 8 GHz down‐conversion mixers using a 0.8 µm SiGe hetero‐junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up‐conversion mixer was implemented on‐chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up‐conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down‐conversion mixer was implemented on‐chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down‐conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.     

Ka-Band Monolithic GaAs Balanced Mixers

Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5x0.43 in. This includes the contribution of a 1.5-dB noise figure due to if preamplifier (5-500 MHz).     

Ka-band monolithic GaAs balanced mixers

Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5 × 0.43 in. This includes the contribution of a 1.5-dB noise figure due to IF preamplifier (5-500 MHz).     

新型四次谐波混频电路

本文介绍了一种适用于高次谐波混频的电路原理图,基于空闲频率相位抵消理论,该混频电路结构可以避免复杂的空闲频率回收电路设计,同时能获得很高的端口隔离度。基于该结构,设计了新型的Ka波段四次谐波混频器,该混频器在38.4 GHz测得最小变频损耗 8.3 dB,在34-39 GHz 变频损耗小于10.3dB, LO-IF、RF-LO、 RF-IF 端口隔离度分别优于30.7 dB、 22.9dB、46.5dB。     

A Simple Method for Millimeter-Wave Finline Balanced Mixer Design Using Three-Dimensional Field Simulation Software

In this paper, a simple method for millimeter-wave finline balanced mixer design using three-dimensional field simulation software has been proposed. The method can be widely used to design the diode-based circuits, especially for the circuit structures with orthogonal field in some specific hybrid integrated circuits which are unavailable to be designed using the circuit simulator. In these circuits, the power directly at diodes is correlated to the input reflection coefficient. The diodes mounted on the finline circuits are defined as impedance boundary in the commercial computer-aided design (CAD) tool High Frequency Structure Simulator (HFSS) model, and hence simulation with the use of HFSS can be implemented to optimize the input matching network of the finline circuits for transferring maximum power to the diodes. Two finline balanced mixers at U-band using commercial GaAs Schottky diodes have been designed and fabricated to validate this method. Matching structures at the radio frequency (RF) port have been employed for a better return loss and a lower conversion loss. Experiment results are presented and show good agreement with simulation data. The proposed method has proven to be useful for the design of millimeter-wave mixers in finline technique.     

Coplanar-waveguide-based terahertz hot-electron-bolometer mixers mproved embedding circuit description

Series-fed coplanar-waveguide embedding circuits have been recently developed for terahertz mixers using, in particular, superconducting devices as sensors. Although these mixers show promising performance, they usually also show a considerable downward shift in the resonating frequency when compared with calculations using simplified models. This effect is basically caused by parasitics due to the extremely small details (in terms of wavelength) of the device and to the connection of the remaining circuitry (i.e., RF filter). In this paper, we present an improved equivalent-network model of such devices that agrees with measured results. We first propose a method to calculate the characteristic impedance and propagation constant of the coplanar waveguide, etched between two semi-infinite media, which connect the receiving slot antennas to the superconducting device. In the formulation, we take into account, for the first time, the radiation power leakage. We then describe the procedure to calculate the reactances due to the detailed geometry of the mixer device and circuit and we correct the input impedance, calculated with a commonly used simplified network. Finally, by comparing our results with a complete set of measured data, for seven mixers in the range between 500 GHz-3 THz, we analyze the features of our model and propose further improvements. Useful guidelines for designing terahertz mixer circuits are also given.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.     

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the chip, which has a compact size of 0.5 mm/spl times/0.47 mm. The circuit covers a radio frequency range from 30 to 40 GHz. At a RF frequency of 35 GHz, an intermediate frequency of 2.5 GHz and a local-oscillator (LO) power of 7.5 dBm, a conversion loss of 4.6 dB, a single-sideband (SSB) noise figure (NF) of 7.9 dB, an 1-dB input compression point of -6 dBm, and a third-order intercept point at the input of 2 dBm were measured. At lower LO power of 0 dBm, a conversion loss of 6.3 dBm and an SSB NF of 9.7 dB were measured, making the mixer an excellent candidate for low power-consuming wireless local-area networks. All results include the pad parasitics. To the knowledge of the authors, this is the first CMOS mixer operating at millimeter-wave frequencies. The achieved conversion loss is even lower than for passive MMIC mixers using leading edge III/V technologies, showing the excellent suitability of digital CMOS technology for analog circuits at millimeter-wave frequencies.