CMOS电荷泵锁相环中鉴频鉴相器的研究与设计

介绍了鉴频鉴相器(PFD)在其发展过程中产生的结构,并对每一种结构的优缺点进行了比较。通过对原有PFD电路结构进行重新设计,在传统D触发器PFD的基础上提出了两种新型PFD:传输门D触发器型PFD和基于锁存器的PFD。电路设计基于TSMC公司的0.18μm CMOS工艺,仿真环境为Candence Spectre,仿真结果显示电路可以工作在2GHz以上频率的应用环境下。相对于传统的PFD,新型PFD工作频率高、几乎无死区,而且具有噪声低、速度快的优点,在高速、低抖动、低噪声PLL中将有广泛的应用前景。     

改进型鉴频鉴相器及电荷泵电路的设计*

本文设计了基于电荷泵架构锁相环电路的两个关键模块—鉴频鉴相器和改进型电流引导电荷泵。基于对扩展鉴相范围和消除死区方法的研究,鉴频鉴相器的性能得以优化。同时,为了保证电荷泵在一个宽输出电压范围内获得良好的电流匹配和较小的电流变化,许多额外的子电路被应用在电路设计中来改进电荷泵的架构。电路采用了标准90 nm CMOS 工艺设计实现并进行测试。鉴频鉴相器鉴相范围的测试结果为-354～354度,改进型电荷泵在0.2～1.1 V的输出电压范围内的电流失配比小于1.1%,泵电流变化小于4%。电路在1.2 V供电电压下的动态功耗为1.3mW。     

4G/5G分组流描述管理及其优化方法

PFD管理方法主要用于解决后向数据相关规则传输过多时出现的负载过大问题,可动态推送PFD和相应计费规则.首先介绍了3GPP pre-R16中4G/5G的PFD管理方法,包括pull mode和push mode两种方法,同时分析了现有方法的不足,并介绍了相应的优化方案.应用新的优化方法,可减少PFDF和PCEF/TDF...     

Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops

This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8/spl times/ the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-/spl mu/m CMOS process exhibit operating frequencies of 1.25 GHz [=1/(8/spl middot/FO-4)] and 1.5 GHz [=1/(6.7/spl middot/FO-4)] for two techniques, respectively, whereas a conventional PFD operates at <1 GHz [=1/(10/spl middot/FO-4)]. The two proposed PFDs achieve a capture range of 1.7/spl times/ and 1.4/spl times/ the conventional design, respectively.     

A simple precharged CMOS phase frequency detector

We propose a simple precharged CMOS phase frequency detector (PFD). The circuit uses 18 transistors and has a simple topology. Therefore, the detector, in a 0.8-μm CMOS process, works up to clock frequencies of 800 MHz according to SPICE simulations on extracted layout. Further, the detector has no dead-zone in the phase characteristic which is important in low jitter applications. The phase and frequency characteristics are presented and comparisons are made to other PFDs. The phase offset of the detector is sensitive to differences of the duty-cycle between the inputs. Mixed-mode simulations are presented of the lock-in procedure for a phase-locked loop (PLL) where the detector is used. Measurements on the detector are presented for a test-chip with a delay-locked loop (DLL) where the phase detection ability of the detector has been verified     

一种补偿宽频带小数N频率合成器中Sigma-Delta整形噪声的新方法

提出了一种部分补偿Sigma Delta调制器整形噪声的新方案.通过在鉴频鉴相器中的延迟时段向无源滤波器中注入补偿电流,最大可实现16dB的噪声补偿.与其他补偿方案相比,文中提出的方案相对简单和易于实现.特别设计了可变延迟的鉴频鉴相器和补偿电流源,并给出了行为级和电路级的仿真结果.     

A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers

提出了一种部分补偿Sigma Delta调制器整形噪声的新方案.通过在鉴频鉴相器中的延迟时段向无源滤波器中注入补偿电流,最大可实现16dB的噪声补偿.与其他补偿方案相比,文中提出的方案相对简单和易于实现.特别设计了可变延迟的鉴频鉴相器和补偿电流源,并给出了行为级和电路级的仿真结果.     

A Modular Phase-Frequency Detector Design with ±2nπ Linear Range of Operation

To extend the linearity range of the phase-frequency detector/charge pump (PFD/CP) circuit, a modular design for a novel PFD architecture is proposed. The new circuit yields a modular extension range of –2N to 2N, where N is an integer representing the order of the PFD/CP extension. The efficacy of the new PFD/CP is demonstrated by the improved frequency acquisition time obtained via closed-loop simulation. Hence, the developed architecture is a good candidate for phase-locked loops requiring the use of PFD/CP with a broad linear range of operation.     

Phase Detectors/Phase Frequency Detectors for High Performance PLLs

Phase Frequency Detectors (PFDs) for use in clock distribution PLLs and Phase Detectors (PDs) for clock recovery PLLs that we have proposed recently to achieve high performance are reviewed and discussed. For the PFD, operating speed limitation and phase detecting characteristics are improved with two kinds of approaches, i.e., gate/logic design and configuration design. For the PD, a simple compensation technique to prevent the deterioration of the phase detecting characteristics by D-F/F and a new PD with delay cell of VCO replica are proposed to reduce the jitter caused by PD. By SPICE simulations and experiments, it is confirmed that the maximum operating speed of PFD is improved to more than twice of conventional one and the jitter caused by PD is reduced to a minimum level.     

Short locking time and low jitter phase-locked loop based on slope charge pump control

A novel structure of a phase-locked loop(PLL) characterized by a short locking time and low jitter is presented,which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector(PFD) to implement adaptive bandwidth control.This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL.First,the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter...     

一种适用于NRZ数据的时钟数据恢复电路

提出了一种基于传统电荷泵锁相环结构的时钟数据恢复电路.采用一种适用于NRZ数据的新型鉴频鉴相器电路,以克服传统鉴频鉴相器在恢复NRZ信号时出现错误脉冲的问题,从而准确地恢复出NRZ数据.同时,对其他电路也采用优化的结构,以提高时钟数据恢复电路的性能.设计的电路可在1.1 V超低电压下工作,适合RF ID等需要低电压、低功耗的系统使用.     

Modeling of voltage output charge-pump phase frequency detector in tuning loops

Resonant inverters mostly employ tuning loops based on a phase-locked-loop (PLL) circuit. Some commercially available PLL chips, frequently used in this application, include a voltage output charge-pump phase frequency detector (CP/PFD) rather than well-known current output CP/PFD, which complicates the analysis of the loop. We present a new model for voltage output CP/PFD and an analysis of a tuning loop using this model. The proposed model employs the resistance multiplication approach, which is applicable for the circuits containing periodically operated switches. It is shown that a voltage output CP/PFD in conjunction with a simple RC low-pass filter can be modeled using a dc voltage source, a phase error controlled resistor, and a capacitor. The theoretical study is verified by experimental results.     

C波段锁相变频器模块

设计了一种采用锁相环技术的C波段变频器模块,其原理是输入的信号与压控振荡器(VCO)信号相混频,产生两个信号频率差的信号,这个信号与差频信号IF进行鉴频鉴相,产生的误差信号经环路滤波送入压控振荡器(VCO)的调谐端完成锁相,这时压控振荡器输出的信号就是需要的信号。采用这种技术,模块输出的有用信号与输入信号泄漏到输出端口的功率比在83dB以上,可以达到较好的效果,同时可有效避免使用体积较大的腔体带通滤波器。     

衰减片提高多脉冲Gm-APD激光雷达的探测性能

从Gm-APD的泊松统计的雪崩探测模型出发,在长死时间情况下,提出了一种提高Gm-APD激光雷达探测性能的方法。利用衰减片控制信号和噪声的强度,实现了多脉冲探测Gm-APD激光雷达的探测概率、虚警概率和测距误差的提高。研究结果表明:随着衰减片透过率的变化,探测概率存在最大值,测距误差存在最小值,将衰减片透过率控制在0.33~0.20之间,探测距离为1.5 km时,探测概率能提高1倍,测距误差可以从m量级提高到cm量级。     

多极化星载合成孔径雷达系统新工作方式及模糊分析

模糊是影响合成孔径雷达 (SAR)图像质量的主要因素之一,多极化星载SAR的系统设计要求尽可能地抑制模糊,提高图像质量。现有的多极化SAR系统极化时分工作方式虽然简单易行,但在高轨道星载条件下系统的距离模糊问题变得十分严重。为了有效地解决这一问题,该文提出极化频分和极化码分两种新的工作方式,并对它们进行了比较。计算表明这两种新的工作方式确实可以提高系统对模糊的抑制程度。     

A blind particle filtering detector of signals transmitted over flat fading channels

A new particle filtering detector (PFD) is proposed for blind signal detection over flat Rayleigh fading channels whose model coefficients are unknown. The detector employs a hybrid importance function and a mixture Kalman filter. It also incorporates an auxiliary particle filtering strategy with a smoothing kernel in the resampling step. Further, by considering practical information of communication systems and the physical interpretation of the adopted second-order autoregressive (AR) channel model, a fully blind particle filtering implementation is developed. The structure of the proposed PFD can be easily adapted to other system requirements. Simulations are provided that demonstrate the performance of the new PFD.     

A Built-in Single Event Upsets Detector for Sequential Cells

A built-in single event upsets (SEUs) detector is presented in this paper. This detector utilizes charge sharing to detect an SEU in a sequential cell, and the detection process is analyzed through Accuro simulations in a 65 nm technology. The normal operation of this detector would not induce obvious performance degradation of the target circuit. Through using this detector, error correction can be achieved based on dual modular redundancy (DMR) while the related power is about 20.4 % lower than that induced by triple modular redundancy (TMR).     

基于极化起伏度的微弱信号检测

本文研究了窄带极化雷达的微弱目标检测问题。首先给出了随机极化波的瞬态极化投影序列(IPPS)相对于任一期望信号的极化起伏度的概念,导出了极化起伏度的统计特性。在此基础上,利用目标散射信号和接收机噪声的IPPS 特性之问的差异,基于极化积累的思想提出了一种基于极化起伏度的微弱目标检测算法,通过合理选择脉冲宽度和接收带宽等参数,可以极大地改善雷达系统的检测性能。对于反隐身、预警和空间探测等应用领域有着重要的指导意义。     

On the performance of a rapid synchronization algorithm for IR‐UWB receivers

Because of the very low signal duty cycles, synchronization is the most critical issue in ultra wideband (UWB) impulse radio (IR) systems. Some effective synchronization schemes like a symbol‐differential (SD) IR‐UWB receiver have been proposed to synchronize received signals rapidly. Yet, SD IR‐UWB receiver is unsuitable for operation in multi‐user environment because of multiple access interference (MAI). By taking advantage of frame‐differential IR‐UWB receivers, we propose a parallel frame‐differential (PFD) IR‐UWB receiver to do so. Our proposed PFD IR‐UWB receiver manifests better immunity against message passing interface and MAI than the SD IR‐UWB. Based on this PFD IR‐UWB receiver, uncertain (search) regions are limited to one frame duration without any symbol‐level synchronization process. Performance of PFD and SD receivers are compared by computer simulations, showing that the proposed PFD receiver not only achieves significant bit error rate performance but also better and more robust results than the SD receiver in this literature. Copyright © 2012 John Wiley & Sons, Ltd.     

Monitoring machine based synthesis technique for concurrent error detection in finite state machines

This paper discusses a new design methodology for concurrent error detection in synchronous sequential circuits based on the use of monitoring machines. In this approach, an auxiliary sequential circuit, called the monitoring machine, operates in lock-step with the main machine, such that any fault in either of the two machines is immediately detected. This methodology is independent of the fault model. It can be applied to FSMs with pre-encoded states and can also be used for ones being synthesised. It also provides a systematic framework for the combined optimisation of the main and monitoring machines, and for exploring tradeoffs in their implementation. The design of monitored sequential circuits is a two-fold problem; namely one of designing an optimal monitoring machine given the main machine, and the other of encoding the main machine states so that the resulting monitoring machine is minimal. This paper formally discusses the design of both the main and monitoring machines and techniques for their combined optimisation. Tradeoffs in their implementation based on selective fault detection are also examined. Through experimental results, it is shown that the proposed synthesis technique is eminently suitable for the design of low-cost sequential circuits with concurrent error detection. The monitoring machine is less costly than the main machine. It is also not identical to it. As a result, a monitored sequential circuit has significantly lower hardware cost and improved fault coverage than previous implementations. Presently at Texas Instruments (India) Ltd., Bangalore, India.