零偏置光电振荡器相位噪声的讨论与分析

光电振荡器(OEO)可以产生低相位噪声的微波信号。在OEO中,MZ调制器(MZM)可以偏置于正交工作点使基频信号的损耗最低,也可以工作于零偏置点从而得到倍频信号。在MZM零偏置的OEO中,利用电分频器将倍频信号分频得到基频信号,从而构建环路振荡器。本文对这2种OEO(MZM正交偏置和MZM零偏置)的相位噪声进行了理论分析。由理论分析可知,MZM零偏置OEO的相位噪声优于MZM正交偏置OEO。根据仿真结果,可以发现MZM零偏置OEO的相位噪声噪底比MZM正交偏置OEO的相位噪声低3 dB。另外,MZM零偏置OEO的振荡模式间隔并不会受到电分频器的影响。     

双反馈晶振和石英谐振器低噪声性能的进一步研究

本文进一步探讨了有关双反馈晶振低噪声性能的问题,着重分析了石英谐振器静电容C_0对双反馈晶振电路Q倍增固子、石英谐振器Q值及净噪特性的影响。为验证上述C_0的影响,也对不同C_0的石英谱振器的相噪特性进行了测量并得到了与分析一致的结果。     

一种低附加相位噪声的频率合成方法

频率源的相位噪声水平直接制约雷达的性能上限,因而低相噪频率合成技术是高性能雷达系统的一项关键技术。现有低相噪频率合成方法常用高次倍频实现,整体性能上严重依赖于低相噪晶振,成本一直居高不下。对此,提出一种低附加相位噪声频率合成方法,即采用最小化链路上附加相位噪声的技术,用普通恒温晶振级联低相噪放大器、梳状谱发生器和锁相环,最终实现低相位噪声的频率合成。实测数据表明,本文方法以100 MHz普通恒温晶振为参考,积分区间[1 kHz, 30 MHz]的时间抖动为11 fs,频率合成在5.8 GHz载波的相位噪声为-119 dBc/Hz@1 kHz,积分区间[1 kHz, 30 MHz]的时间抖动为13.7 fs,总附加时间抖动为8.17 fs,附加相位噪声仅1.9 dB,达到了业界领先水平,能够有效提升毫米波雷达系统的成像性能,优于传统频率合成方法。     

A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180 nm CMOS Mixed-Signal process while it operates under 1.8 V supply voltage. The measured output frequency of PLL is 1.571 GHz and output power is −1.418 dBm. The in-band phase noise is −98.1 dBc/Hz @ 100 kHz, while the out-band phase noise is −130.3 dBc/Hz @ 1 MHz. The reference spur is −75.8 dBc at 16.368 MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2 μs.     

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigma-delta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the in-band phase noise reduction of the sigma-delta frequency synthesizer. Xiaojian Mao was born in Jiangsu Province, China, in 1978. He received the B.S. degree in electronic engineering from Jilin University, Changchun, China, in 2000. He is currently pursuing the Ph.D. degree in circuits and systems at Department of Electronic Engineering of Tsinghua University, Beijing, China. His current research includes frequency synthesizers and phase-locking and clock recovery for high-speed data communications. And His PhD thesis title is “Design and Analysis of Sigma-Delta Fractional-N PLL Frequency Synthesizer.” Huazhong Yang received BS, MS, and PhD Degrees in electronics engineering from Tsinghua University, Beijing, in 1989, 1993, and 1998, respectively. He is a Professor and Head of the Circuits and Systems Division in the Department of Electronic Engineering at Tsinghua University, Beijing. His research interests include CMOS radio-frequency integrated circuits, VLSI system structure for digital communications and media processing, low-voltage and low-power circuits, and computer-aided design methodologies for system integration. He has authored and co-authored 6 books and more than 100 journals and conference papers. He was the winner of Chinas National Palmary Young Researcher Award in 2000. Hui Wang received the B.S. degree from Department of Radio Electronics, from Tsinghua University, Beijing, China. She was a visiting scholar at Stanford University, CA, USA from February 1991 to September 1992. Currently she is a Professor of the Circuits and Systems Division in the Department of Electronic Engineering and the deputy dean of academic affairs office at Tsinghua University, Beijing, China. Her research interests include modeling and simulation of radio-frequency CMOS integrated circuits, automatic design methodology for low voltage and low-power integrated circuits, and interconnect modeling and synthesis for deep submicron system-on-a-chip. She has authored and co-authored 4 books and over 70 papers. She was a primary research of TADS-C4 which gained a third-grade prize for the national progress in science and technology in China in 1993.     

一种带有开关电流源的低相噪压控振荡器

提出一种带有开关电流源的电感电容压控振荡器（LC VCO）。该技术通过反馈电容将电感电容压控振荡器的输出耦合到电流源,形成了电流源的开关特性,从而减小了电感电容压控振荡器的相位噪声。提出的电感电容压控振荡器采用华虹 NEC的0.18μm SiGe BiCMOS工艺,工作频率为5.7 GHz,相位噪声为-113.0 dBc/Hz@1MHz,功耗为2.3 mA。在其他性能相同的情况下,提出的电感电容压控振荡器的振荡频率比典型的电感电容压控振荡器的相位噪声小4.5 dB。     

低相噪毫米波频率合成器设计

简要介绍毫米波频率合成器的重要性,分析两种毫米波频率合成器实现方案的优劣,综合其优点,并采用直接数字频率合成（DDS）技术,提出毫米波频率合成器的设计方案。进行方案系统实验,结果表明,相位噪声为-85dBc／Hz@10kHz,提升了整个毫米波通信系统的性能。     

Traps centers impact on Silicon nanocrystal memories given by Random Telegraph Signal and low frequency noise

This work reports on a comprehensive process of trapping centers in Silicon nanocrystal (nc-Si) memories devices. The trap centers have been studied using Random Telegraph Signal (RTS) and Low Frequency (LF) techniques. The study of the traps which are responsible for RTS noise in non-volatile memories (NVM) devices as a function of gate voltage and temperature, offers the opportunity of studying the trapping/detrapping behaviour of a single interface trap center. The RTS parameters of the devices having random discrete fluctuations in the drain current get more information about trap energy level and spatial localization from the SiO₂/Si interface. The impact of trap centers has been also investigated showing the significant noise between memories and references devices. Furthermore, it has convincingly been shown that this discrete switching of the drain current between a high and a low state is the basic feature responsible for l/f^γ flicker noise in MOSFETs transistors.     

一种双控制回路低相位噪声CMOS压控振荡器设计

在集成锁相环中，压控振荡器的输出频率范围要能随所有工艺和工作条件的变化而覆盖所需的频率范围。增大压控振荡器的增益而实现宽调协范围会增加压控振荡器和锁相环的相位噪声。在这篇文章中，通过两路控制来得到压控振荡器中心频率可调，实现了非常小的压控振荡器增益。     

A dual-band frequency synthesizer for CMMB application with low phase noise

A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA cu...     

一种应用于CMMB的双频段低噪声频率合成器

A wide-band frequency synthesizer with low phase noise is presented. The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range. This PLL is fabricated with 0.35 μ m SiGe BiCMOS technology. The measured result shows that the RMS phase error is less than 1^o and the reference spur is less than –60 dBc. The proposed PLL consumes 20 mA current from a 2.8 V supply. The silicon area occupied without PADs is 1.17 mm².     

基于Rb原子频标电注入锁定的高频稳低相噪光电振荡器

为了进一步改善光电振荡器(OEO)输出信号频 率的长期稳定度和相位噪声,提出了一种基于 Rb原子频标电注入锁定的单环OEO。将Rb原子钟产生的高频稳正弦信号注入到单环OEO,通过 注入信号与自由振荡信号的频率牵引,OEO获得单一振荡模式。实验发现,随着注入功 率的 增大,锁定带宽变大,锁定信号的相位噪声变差;随着注入功率的下降,锁定带宽变小,锁 定信号的相位噪声得 到改善,趋近于注入源信号的相位噪声。当光纤长取10km时,获得 了中心频率10GHz、边模抑制比大 于60dB、相位噪声的指标为－76dBc/Hz@100Hz和－108dBc/Hz@10kHz的输出信号,其输 出信号的长期稳定度和准确度得到改善。实验结果与理论分析一致。     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

一种新型的宽带低相位噪声2分频器

通过对各种2分频器结构的研究,提出一种新结构的D触发器。由此触发器组成的2分频器具有宽带低相位噪声的特点。与传统的动态SCL结构的D触发器相比,通过在D触发器的输入对管的耦合端口和时钟端口之间加一个开关管,扩展了工作带宽并同时保持了低的相位噪声。此芯片采用IBM 的90nm CMOS工艺。测试结果表明,此2分频器工作的频率范围为：0.05-10GHz。工作频率为10GHz时,输出信号的相位噪声在频偏1MHz处为-159.8 dBc/Hz 。工作电压为1.2V,功耗为9.12mW。核心芯片面积仅为0.008mm2。     

A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider.Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques,the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area.     

脉冲抽样法测量低频相位差

介绍了一种用脉冲抽样法测量低频相位差的技术。这种技术以可编程逻辑门阵列(FPGA)和单片机为核心,测量的精度达到0.1°。和传统的测相法比较,这种测量方法最大的优点是省去了大量的硬件电路,特别是省去了对速度和漂移特性要求苛刻的整形电路,也省去了鉴相电路、大小相角判别电路,只需增加一个抽样保持电路,给设计、调试带来了方便,而且,这种测量没有传统意义的幅相误差,给整机性能的稳定性和一致性带来了好处。     

基于双环X波段低相噪频率合成器的设计与实现

基于相位噪声特性,对数字锁相式频率合成器进行了研究和分析。在对比传统单环锁相技术的基础上,介绍了一种双环技术的X波段低相噪锁相式频率合成器。在满足小频率步进、低杂散的情况下,设计所得到的X波段频率合成器其绝对相位噪声≤-100 dBc/Hz@1 kHz。     

Joint MAP channel estimation and data detection for OFDM in presence of phase noise from free running and phase locked loop oscillator

This paper addresses a computationally compact and statistically optimal joint Maximum a Posteriori (MAP) algorithm for channel estimation and data detection in the presence of Phase Noise (PHN) in iterative Orthogonal Frequency Division Multiplexing (OFDM) receivers used for high speed and high spectral efficient wireless communication systems. The MAP cost function for joint estimation and detection is derived and optimized further with the proposed cyclic gradient descent optimization algorithm. The proposed joint estimation and detection algorithm relaxes the restriction of small PHN assumptions and utilizes the prior statistical knowledge of PHN spectral components to produce a statistically optimal solution. The frequency-domain estimation of Channel Transfer Function (CTF) in frequency selective fading makes the method simpler, compared with the estimation of Channel Impulse Response (CIR) in the time domain. Two different time-varying PHN models, produced by Free Running Oscillator (FRO) and Phase-Locked Loop (PLL) oscillator, are presented and compared for performance difference with proposed OFDM receiver. Simulation results for joint MAP channel estimation are compared with Cramer-Rao Lower Bound (CRLB), and the simulation results for joint MAP data detection are compared with “NO PHN” performance to demonstrate that the proposed joint MAP estimation and detection algorithm achieve near-optimum performance even under multipath channel fading.     

Averaging of phase noise in PSK signals by an opto-electrical feed-forward circuit

This paper proposes an opto-electrical feed-forward circuit that reduces phase noise in binary PSK signals by averaging the noise. Random and independent phase noise is averaged over several bit slots by externally modulating a phase-fluctuating PSK signal with feed-forward signal obtained from signal processing of the outputs of delay interferometers. The simulation results demonstrate a reduction in the phase noise.     

超宽带低相噪频率合成器的实现

介绍了1种频率范围4~16GHz,步进1MHz的超宽带、小步进、低相噪频率合成器的实现方法。通过混频式锁相环方案,大大降低了环内分频比,选用低相噪器件,以及采用了梳状谱发生器代替传统的大步进环等措施,使输出实现了低相噪指标。在16GHz输出时,相位噪声指标小于-90dBc/Hz(@10kHz)。并通过对合成器指标的分析,阐述了在混频环设计过程中需要注意的一些问题。