Generating a family of testable designs using the BILBO methodology

There are usually many different ways to make a digital circuit testable using the BILBO methodology. Each solution can have different values of test time and area overhead. A design system based on the BILBO methodology has been developed that can efficiently explore the testable design space to generate a family of designs ranging from the minimal test time design to the minimal area overhead design. A designer can select an appropriate design based on trade-offs between test time and area overhead. The branch and bound technique is employed during the exploring process to prune the design space. This significantly reduces the execution time of this process. To effectively bound the exploring process, a very efficient test scheduler has been developed. Unlike previous approaches, this new test scheduler can process a partially testable design as well as a complete testable design. A test schedule for a design is constructed incrementally. The test scheduling procedures are presented along with experimental results that show that this test scheduler usually outperforms existing schedulers. In many cases, it generates an optimal test schedule. Experiments have been performed on several circuits generated by MABAL, a CAD synthesis tool, to demonstrate the performance and practicality of this system.This work was supported by the Defense Advanced Research Projects Agency and monitored by the Federal Bureau of Investigation under Contract No. JFBI90092. The views and conclusions considered in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government.     

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

A decomposition approach for testing large analog networks

This article presents an efficient method for testing large scale analog and mixed mode networks. Test equations are derived for a partitioned network from Krichhoff current law equations at the partition points. Voltages at the partition points are used to identify network parameters. The method has applications to circuit modeling, fault diagnosis, testing and calibration. The conventional testing methods for dynamic, nonlinear networks are based on the sensitivity approach, which uses incremental changes in voltages to estimate changes in network parameters. However, this conventional approach cannot handle large scale circuits because the sensitivity matrix is dense. This results in enormous requirements for memory space and computing time when the circuit size becomes large. The new method overcomes these deficiencies of the sensitivity approach. In this article, we introduce the decomposition method, describe its basic features and its algorithm, and compare this method with a conventional, sensitivity technique using testing network examples.This work was supported in part by the National Institute of Standards and Technology, U.S. Department of Commerce, Under Grant No. 70NANBGH0662.     

Analysis of Manufacturability Factors for Analog CMOS ADC Building Blocks

In this paper, the layout of analog CMOSintegrated circuits is considered as one of the mostimportant manufacturability factors. Various layoutdesign styles are introduced and applied to the physicaldesign of latched comparators and A/D converter buildingblocks. In the following examination, post-layoutsimulation results are discussed and compared withmeasurement of the A/D circuits that were fabricated in a0.35 m digital CMOS process. It is shown in thispaper that different circuit layout styles can result insignificant differences in circuit performance.Additionally, it is shown that the layout-relatedperformance variability is attributed to statisticalprocessing variations.     

Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

Cell Fault Model (CFM) is a well-adopted functional fault model used for cell-based circuits. Despite of the wide adoption of CFM, no test tool is available for the estimation of CFM testability. The vast majority of test tools are based on the single stuck-at fault model.In this paper we introduce a method to calculate the CFM testability of a cell-based circuit using any single stuck-at fault based test tool. Cells are substituted by equivalent cells and Test Generation and Fault Simulation for CFM are emulated by Test Generation and Fault Simulation for a set of single stuck-at faults of the equivalent cells. The equivalent cell is constructed from the original cell with a simple procedure, with no need of knowledge of gate-level implementation, or its function. With the proposed methodology, the maturity and effectiveness of stuck-at fault based tools is used in testing of digital circuits, with respect to Cell Fault Model, without developing new tools.     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

实用BiCMOS电路可测性设计

本文提出了ＢｉＣＭＯＳ电路的实用可测性设计方案，该方案与传统方法相比，可测性高，硬件花费小，仅需额外添加两个ＭＯＳ管和控制端，就可有效地用单个测试码测出ＢｉＣＭＯＳ电路的开路故障和短路故障，减少了测试生成时间，可广泛应用于集成电路设计中。     

Tutorial on semiconductor memory testing

This article is a tutorial introduction to the field of semiconductor memory testing. It begins by describing the structure and operation of the main types of semiconductor memory. The various ways in which manufacturing defects and failure mechanisms can cause erroneous memory behavior are then reviewed. Next we describe the different contexts in which memories are tested together with the corresponding different types of tests. The closely related processes of fault modeling and test development are then summarized. Various design for testability strategies for memories are also presented. Finally, current trends in the design and testing of memory are outlined.This work was supported by the Natural Sciences and Engineering Research Council of Canada under grant OGP 0105567.     

ASIC可测试性设计技术

可测性设计技术对于提高军用ＡＳＩＣ的可靠性具有十分重要的意义。结合可测性设计技术的发展,详细介绍了设计高可靠军用ＡＳＩＣ时常用的ＡｄＨｏｃ和结构化设计两种可测性技术的各种方法,优缺点及使用范围。其中,着重论述了扫描技术和内建自测试技术。     

一种智能卡电性能可靠性的测试方法

随着智能卡以其自身高效、安全、便捷的特点在众多领域的应用,人们对其可靠性的要求也越来越高,因此有效的可靠性测试显得尤为重要.本文主要以接触式智能卡为例针对智能卡可靠性测试的一方面--电性能测试提出一种方便可行的测试方法.该方法在总结智能卡测试方法标准ISO/IEC10373的基础上,改进了相关测试项测试方法,根据实际情况补充了漏灌电流测试并详细说明其测试方法.根据测试需要设计了电性能全覆盖测试的程序,自动生成电性能测试报告.     

基于二分图模型的通信信息网络故障联合定位

国家电网信息通信网络依靠两套运维系统,分别实现对信息网络与通信网络的故障定位与分析,然而通信网络故障往往会引发信息网络故障,如何高效精确地进行通信信息网络故障联合定位是亟需解决的问题.针对信息通信网络的联合故障定位问题,提出了基于二分图模型的故障联合定位算法.首先依据通信网网络节点的关联性对网络分簇,并将每一簇作为一个子域.其次在每个子域内建立基于二分图的故障关联影响模型,最终利用目标排序法并行地对多个子域内网络故障进行分析,从而实现通信信息网络关联故障高效精确的联合定位.实验结果表明,该联合故障定位分析方法的故障诊断率达85％～95％.     

Noise-Insensitive Digital BIST for any PLL or DLL

PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, phase error, output frequency, duty cycle, lock time, and lock range. Two techniques for cancelling random and systematic noise are also described. The multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.

Design of a C-testable booth multiplier using a realistic fault model

A Booth multiplier is the most widely used type of multiplier. In this article, the testability issues involved in its design are discussed. In contrast to previous work, the fault model includes not only node stuck-at faults, but also transistor stuck-open and stuck-close faults. Moreover, as a result of adopting a hierarchical testability approach, the designed Booth multiplier turns out to be fully C-testable. To achieve this C-testability, only three additional controllable inputs are required, which results in a negligible area and delay overhead.Currently with Alcatel Bell Telephone.     

基于SOM神经网络的航舵故障分类方法

为解决航舵故障诊断的复杂非线性模式分类问题,提出一种基于自组织特征映射(SOM)神经网络的航舵故障诊断方法,构造一个2层SOM神经网络,训练后多个权值向量位于输入向量聚类中心,实现快速有效的自适应分类.仿真结果表明:SOM网络经过100次训练即可实现聚类,对有限故障测试样本分类准确率可达90％,对航舵故障诊断具有一定的参考价值.     

一种超前进位加法器的新颖BIST架构

针对超前时进位加法器（CLA），提出了一种高效的BIST架构。这种新的架构结合了确定性测试和伪随机测试的优点，并避免了各自的短处。同时，还提出了一个测试向量集，并充分利用了CLA加法器内部结构的规整性，向量集规模较小，便于片内集成。最后，提出了一种计算特征值的新方法。     

基于扫描的VLSI全速测试方法

当工艺进入到超深亚微米以下,传统的故障模型不再适用,必须对电路传输延迟引发的故障采用延迟故障模型进行全速测试.给出了常用的延迟故障模型,介绍了一种基于扫描的全速测试方法,并给出了全速测试中片上时钟控制器的电路实现方案.对芯片进行测试,可以直接利用片内锁相环电路输出的高速时钟对电路施加激励和捕获响应,而测试向量的扫描输入和响应扫描输出则可以采用测试机提供的低速时钟,从而降低了全速测试对测试机时钟频率的要求.最后,对于全速测试方案提出了若干建议.     

Fault macromodeling and a testing strategy for opamps

In this paper, we propose a simple testing technique based on DC measurements for operational amplifiers. We first develop a comprehensive macromodel for the transistor-level opamp to alleviate the efforts of fault simulation. By incorporating appropriate I/O characteristics into the macromodel, the output deviation due to the modeling error can be significantly reduced. We use the transistor short/bridging faults to illustrate the efficiency of our proposed technique. Experimental results show that a high fault coverage can be achieved for the stand-alone opamp by measuring two DC parameters V _o-max ^* and V _o-min ^*. For the embedded opamps, many short/bridging faults cannot be detected by traditional functional testing. However, by using similar DC measurements along with a design for testability (DFT) scheme, we can improve the fault coverage dramatically.An earlier version of this work was reported in ICCAD-94.     

An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures

In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy, exploiting the regularity and modularity of the VLIW-TTA structure, remains general for an arbitrary application and instantiation of the TTA processor and is based on the partial scan approach along with the functional test. The test-time analysis, in order to justify our approach and show the superiority over the classical full-scan, has been performed. The results of our strategy are shown in a few examples at the end of the paper.     

微处理器系统功能测试

针对微处理器系统测试问题，提出了一种全新的功能测试方法。详细介绍了该方法的硬件组成和测试生成。该方法以结构故障模型为基础，将数字电路故障分为3大类6种故障，分另4为固定型故障、开路型故障和短路型故障3种，其中固定型故障又可分为固定0和固定1两种，开路故障分为开路为0、开路为1以及开路为Z三种。为了验证该方法的有效性，本文针对一块以MC6800为微处理器的电路板进行了测试程序开发。实验结果表明，故障覆盖率取得了满意的结果。     

CMOS IC漏极静态电流测试技术的现状与发展

全面介绍了CMOS集成电路漏极静态电流(IDDQ)测试技术的现状、应用及其发展趋势。与其它主要用于检测逻辑功能的测试技术不同，IDDQ主要用于检测电路的物理缺陷和工艺故障。作为逻辑功能测试的重要补充，IDDQ技术可提高集成电路的可测性和故障覆盖率，保证集成电路的可靠性。