Static characteristics of extremely thin gate oxide m.o.s. transistors

The drain current of an extremely thin gate oxide m.o.s. transistor shows an exponential dependence both on drain voltage and gate voltage, even in the `postthreshold? region. The input gate current of a device with 20 ? gate oxide is estimated to be negligible for a logic-circuit operation with 0.2 V supply voltage.     

Partially depleted SOI MOSFETs under uniaxial tensile strain

The effects of tensile uniaxial strain on the DC performance of partially-depleted silicon-on-insulator n and p-channel MOSFETs as a function of orientation and gate length are reported. The drain current of the n-MOSFETs increases for both longitudinal and transverse strain orientations with respect to the current flow direction. In the n-MOSFET, longitudinal strain provides greater enhancement than transverse strain. In contrast, for p-MOSFETs, longitudinal strain decreases the current while transverse strain increases the drain current. The magnitude of the fractional change in drain current decreases as gate length is reduced from 20 to 0.35 /spl mu/m. These phenomena are consistent with those of bulk silicon MOSFETs and are shown to be qualitatively correlated with the piezoresistance coefficients of the Si inversion layer. Analysis of the linear drain current versus gate voltage characteristics shows that the threshold voltage is independent of strain while the change in drain current tracks with the change in effective electron and hole mobility. Closer examination shows that as the gate length is reduced from 20 to 0.35 /spl mu/m, the relative increase in low-field electron and hole mobility is constant for transverse strain and generally decreases with gate length for longitudinal strain.     

A one-dimensional theory on the effects of diffusion current and carrier velocity saturation on E-type IGFET current-voltage characteristics

Current-voltage characteristics of an enhancement-type insulated gate field-effect transistor (E-type IGFET) are analyzed based on a one-dimensional model, taking account also of the diffusion current component. Explicit formulae for the entire I-V characteristic curve are given. The solution for the triode characteristic shows considerable deviation from “drift current theory” in terms of turn-on voltage (or threshold voltage) and drain voltage at just saturation. The solution for the pentode characteristic taking account of carrier's saturation velocity, shows that the increase in drain current per unit drain voltage is larger in short-channel devices than in long-channel devices. Agreement with experiment is very good.     

Subthreshold current in MODFETs of tenth-micrometer gate

The subthreshold current of conventional GaAs/AlGaAs MODFETs and pseudomorphic InGaAs/AlGaAs MODFETs with the gate length down to 0.12 μm is investigated. The gate swing increases with the drain voltage and decreases with the gate length. It is attributed to charge injection from source to drain, limited by the channel potential barrier, which is a function of both the drain and the gate voltages. The pseudomorphic InGaAs/AlGaAs MODFETs show much better control than the conventional GaAs/AlGaAs MODFETs for the subthreshold current, especially with high drain biases. This shows that the pseudomorphic quantum-well structures can suppress the subthreshold current passing through the GaAs buffer region and reduce the undesirable short-channel effects     

Resistive gate DMOST for low distortion mixing

A new device for mixing in the VHF range is presented which has very low third-order distortion. The device consists of a DMOST having a polysilicon resistive gate which is biased by a d.c. current that flows at right angles to the source to drain current in the DMOST. As a result of this gate bias current the device has a drain current to input gate voltage characteristic with a large square low region when the drain operates above the “pinch off” voltage. Samples of the device exhibit an extremely quadratic behaviour over several volts of the input gate voltage.     

GaAs微波功率FET的可靠性与功率特性的关系

采用射频最大饱和漏电流和射频击穿电压解释了影响GaAs微波功率FET功率特性的主要因素,GaAs FET栅漏间半导体表面负电荷的积累在引起器件电流偏移的同时还导致器件微波功率特性的退化,GaAs微波功率FET的可靠性和功率特性相互关联,高可靠的GaAs微波功率FET一定具有高性能的功率特性。在器件工艺中对表面态密度和陷阱能级密度严格控制是实现GaAs微波功率FET的高功率特性和高可靠性的关键。     

Electron gate currents and threshold stability in the n-channel stacked gate MOS tetrode

A new structure is given for the n-channel stacked gate MOS tetrode which consists of a polycrystalline silicon buried control gate and thermally grown oxide for the offset gate insulator. As a result of the large band-bending in the offset gate depletion region of an operating tetrode, some drain current electrons surmount the Si-SiO2energy barrier and are injected into the oxide. Since the electron trapping is relatively small in the thermal-oxide offset gate insulator, it was possible to measure gate currents of up to2 times 10^{-4}A/cm². The gate current was measured as a function of the drain current, the drain voltage and the offset gate voltage. The resulting behavior confirms previous models of the tetrode device. Since electron trapping is much less in thermally grown oxide than in deposited pyrolytic oxide which was used formerly, the offset gate threshold voltage shifts less. As a result of this effect the new structure is used to advantage in fabricating the n-channel stacked gate tetrode in that the drain current is comparatively insensitive to changes in the offset gate voltage.     

A large-signal switching MESFET model for intermodulationdistortion analysis

This paper describes an improved large-signal model for predicting an intermodulation distortion (IMD) power characteristic of MESFETs in switching applications. The model is capable of modeling the voltage-dependent drain current and its derivatives, including gate-source and gate-drain capacitors. The drain current and its derivatives are described by a function of a voltage-dependent drain conductance. The model parameters are extracted from a measured drain conductance versus gate voltage characteristic of a MESFET. This paper also presents a new fully symmetric equivalent circuit for switching MESFETs. The IMD power characteristics calculated with the use of the proposed method are compared with experimental data taken from a monolithic microwave integrated circuit single-pole double-throw switch. Good agreements over the large gate voltages and input power levels are observed     

Microwave power double-heterojunction HEMT's

The RF and dc characteristics of microwave power double-heterojunction HEMt's (DH-HEMT's) with low doping density have been studied. Small-signal RF measurements indicated that the cutoff frequency and the maximum frequency of oscillation in DH-HEMT's with 0.8-1 µm gate length and 1.2 mm gate periphery are typically 11- 16 GHz and 36-41 GHz, respectively. However, the cutoff frequency in DH-HEMT's degrades strongly with increasing drain bias voltage. This may be caused by both effects of increasing effective transit length of electrons and decreasing average electron velocity, due to Gunn domain formation. In large-signal microwave measurement, the DH-HEMT (2.4 mm gate periphery) delivered a maximum output power of 1.05 W with 2.8 dB gain and 0.58 W with 1.6 dB gain at 20 and 30 GHz, respectively. These are the highest output powers yet reported for HEMT devices. For the dc characteristics, the onset of two-terminal gate breakdown voltage is found to correlate with the drain current Idssand recessed length, and three-terminal source-drain breakdown characteristics near pinchoff are limited by the gate-drain breakdown. A simple model on gate breakdown voltage in HEMT is also presented.     

A new gate current extraction technique for measurement of on-statebreakdown voltage in HEMTs

We present a new simple three-terminal technique for measuring the on-state breakdown voltage in HEMTs. The gate current extraction technique involves grounding the source, and extracting a constant current from the gate. The drain current is then ramped from the off-state to the on-state, and the locus of drain voltage is measured. This locus of drain current versus drain voltage provides a simple, unambiguous definition of the on-state breakdown voltage which is consistent with the accepted definition of off-state breakdown. The technique is relatively safe and repeatable so that temperature dependent measurements of on-state breakdown can be carried out. This helps illuminate the physics of both off-state and on-state breakdown     

Frequency doubling in GaAs/AlGaAs field effect transistor usingreal space transfer

A modified field effect transistor (FET) topology is used which enhances the real space transfer of carrier out of the channel toward a special collector terminal. The drain current rises, peaks, and then reduces as gate voltage is increased due to a steep rise in collector current with gate voltage. When biased near the peak, the AC drain current induced by the gate is folded over becoming frequency doubled. The device exhibits functional multiplexing being operable as either a positive transconductance, negative transconductance, or frequency doubling element setable via quiescent gate voltage     

Trapping effects and microwave power performance in AlGaN/GaN HEMTs

The dc small-signal, and microwave power output characteristics of AlGaN/GaN HEMTs are presented. A maximum drain current greater than 1 A/mm and a gate-drain breakdown voltage over 80 V have been attained. For a 0.4 μm gate length, an f_T of 30 GHz and an f_max of 70 GHz have been demonstrated. Trapping effects, attributed to surface and buffer layers, and their relationship to microwave power performance are discussed. It is demonstrated that gate lag is related to surface trapping and drain current collapse is associated with the properties of the GaN buffer layer. Through a reduction of these trapping effects, a CW power density of 3.3 W/mm and a pulsed power density of 6.7 W/mm have been achieved at 3.8 GHz     

High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm

High-performance inversion-type enhancement- mode (E-mode) n-channel In_0.65Ga_0.35As MOSFETs with atomic-layer-deposited Al₂O₃ as gate dielectric are demonstrated. A 0.4-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 10 nm shows a gate leakage current that is less than 5 times 10^-6 A/cm² at 4.0-V gate bias, a threshold voltage of 0.4 V, a maximum drain current of 1.05 A/mm, and a transconductance of 350 mS/mm at drain voltage of 2.0 V. The maximum drain current and transconductance scale linearly from 40 mum to 0.7 mum. The peak effective mobility is ~1550 cm²/V ldr s at 0.3 MV/cm and decreases to ~650 cm²/V ldr s at 0.9 MV/cm. The obtained maximum drain current and transconductance are all record-high values in 40 years of E-mode III-V MOSFET research.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Device reliability study of AlGaN/GaN high electron mobility transistors under high gate and channel electric fields via low frequency noise spectroscopy

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel.     

New degradation mechanism observed for AlGaN/GaN HEMTs with sub 100 nm scale unpassivated regions around the gate periphery

AlGaN/GaN HEMTs with low gate leakage current in the μA/mm range have been fabricated with a small-unpassivated region close to the gate foot. They showed considerably higher critical voltage values (average VCR = 60 V) if subjected to step stress testing at OFF-state conditions and room temperature as compared to standard devices with conventional gate technology. This is due to the fact that electrons injected from the gate can be accumulated at the unpassivated region and thus builds up negative charge. The lower gate leakage is due to virtual gate formation, which is reducing local electric field in the vicinity of the gate. In contrast to devices with standard gate technology, degradation during step stressing is not associated with a simultaneous gate leakage and drain leakage current increase but with a strong increase of drain current at OFF-state conditions while the gate leakage is practically not affected. Then a relatively higher critical voltage of around 60 V is achieved. An abrupt increase of subthreshold drain current implies the formation of a conductive channel bypassing the gate region without influencing gate leakage. It is believed that hopping conductivity via point defects formed during device stressing creates this channel. Once this degradation mode takes place, the drain current of affected devices significantly drops. This can be explained by negative trap formation in the channel region affecting the total charge balance in 2DEG region. Electroluminescence measurements on both fresh and degraded devices showed no hot spots at OFF-state conditions. However, there is additional emission at ON-state bias, which suggests additional energetic states that lead to radiative electron transition effects in the degraded devices, most possibly defect states in the buffer.     

Drain conductance of junction gate FET's in the hot electron range

A new model is proposed for the drain conductance of J-FET's in the hot electron range. The model is based on a physical picture revealed through two-dimensional numerical analysis. The two-dimensional analysis shows that the electron concentration changes gradually at the boundary of a depleted region which is defined by a conventional theory. Because of this gradual change, electrons can remain after the pinch-off and contribute to the drain current. Although the high electric field causes the electron velocity to saturate, the drift velocity vector rotates into the x axis (source-to-drain) with the increase in the drain voltage. The increase in the x component Vxof the drift velocity gives rise to a small increase in drain current, that is, a finite drain conductance. The proposed model takes into account the above two essential features, gradual change in electron distribution, and the rotation of the velocity vector. This model is constructed in a single formulation which describes the current-voltage characteristics from the linear to the saturated drain-current region. Theoretical calculations agree quite well with the experiment on GaAs Schottky barrier gate FET's.     

A novel 4H-SiC MESFET by lateral insulator region to improve the DC and RF characteristics

In this paper, a novel recessed gate metal–semiconductor field-effect transistor (RG-MESFET) is presented by modifying the depletion region and the electric field. The proposed structure improves the breakdown voltage, drain current and high frequency characteristics by embedding a lateral insulator region between drain and gate while is placed laterally into the metal gate and a silicon well exactly under the insulator region. We called this new structure as modified recess gate MESFET (MRG-MESFET). The radio frequency and direct current (DC) characteristics of the proposed structure is studied using numerical simulations and compared with a conventional MESFET (C-MESFET). The breakdown voltage, drain current DC transconductance and maximum power density of the proposed structure increase by 27%, 16.5%, 15% and 48%, respectively, relative to the C-MESFET. Also, the gate-source capacitance and the minimum noise figure of the proposed structure improve relative to the C-MESFET. The proposed structure can be used for high breakdown voltage, high saturation drain current, high DC transconductance, high power, high frequency, and low noise applications.     

The resonant-tunneling field-effect transistor: A new negative transconductance device

A new field-effect transistor with a resonant-tunneling barrier in the gate is presented. The gate and the drain currents versus gate voltage exhibit peaks when the resonant-tunneling gate current is quenched. Thus, in addition to negative differential resistance, this structure also exhibits negative transconductance, a unique feature in an n-channel device. Also, by proper gate bias, the same resonance of the double barrier can be used to produce two peaks in the drain current versus drain voltage characteristic at nearly the same current level. This is a very desirable feature for many applications.     

一种测试功率MOSFET热阻的新方法

阐述了一种测试功率MOSFET热阻的新方法。该方法选取漏源电流作为温度敏感参数,在相同漏源电压和栅源电压幅度下,当栅源电压条件由直流形式变为脉冲形式时,漏源电流是有差异的,这一差异是由结温的不同造成的。而脉冲栅源电压下环境温度的调整可以用来模拟直流条件下的结温,由此可以测得器件在直流条件下的热阻。该方法具有精度高、实现容易和操作方便等优点,可作为功率MOS器件结温和热阻的有效测试方法。