A GaAs gate heterojunction FET

A new semiconductor-insulator-semiconductor field-effect transistor has been fabricated. The device consists of a heavily doped n-type GaAs gate with undoped (Al,Ga)As as the gate insulator, on an undoped GaAs layer. This structure gives the device a natural threshold voltage near zero, well suited for low-voltage logic. The threshold voltage is, to first order, independent of Al mole fraction and thickness of the (Al,Ga)As layer. The layers were grown by MBE and devices fabricated using a self-aligned technique involving ion-implantation and rapid thermal annealing. A transconductance of 240 mS/mm and a field-effect mobility of about 100 000 cm²/V-s were achieved at 77 K.     

A novel GaAs FET with double camel-like gate structure

Extremely high potential barrier height and gate turn-on voltage of a novel GaAs field-effect transistor with n/sup +//p/sup +//n/sup +//p/sup +//n double camel-like gate structure are demonstrated. The maximum electric field and potential barrier height of the double camel-like gate are substantially enhanced by the addition of another n/sup +//p/sup +/ layers in gate region, as compared with the conventional n/sup +//p/sup +//n single camel-like gate. For a 1/spl times/100 /spl mu/m/sup 2/ device, a potential barrier height up to 2.741 V is obtained. Experimentally, a high gate turn-on voltage up to +4.9 V is achieved because two reverse-biased junctions of the double camel-like gate absorb part of positive gate voltage. In addition, the transistor action shows a maximum saturation current of 730 mA/mm and an extrinsic transconductance of 166 mS/mm.     

A new heterojunction gate GaAs FET

A new type of GaAs JFET having a heterojunction gate is proposed. The structure involves epitaxially grown layers of n-GaAs for the channel and of p-GaAlAs for the gate which can be easily delineated by the self-alignment technology using an overgrown p-GaAs. The potential advantages of the heterojunction structure for GaAs FET's over the conventional Schottky barrier are in the fewer masks for fabrication and the short channels expected. Some preliminary experimental results on fabrication technologies and dc characteristics of the new devices are described.     

Direct-coupled logic operation of GaAs column gate FET

A ring oscillator operation is demonstrated employing normally-off 2 µm diameter column gate FET with 145 ps/gate delay time and with 64 fJ power-delay product. Delay time is discussed in terms of CR time constant comparison between MES and column structure. The column gate FET can realize much smaller "on" resistance comparing with MESFET.     

MIM gate FET: new GaAs enhancement-mode transistor

A new type of GaAs FET, the metal-insulator-metal gate FET, is proposed, which combines the advantages of both the GaAs MESFET and the GaAs MISFET. The device is especially suitable for the enhancement mode of operation.     

A flip-chip GaAs power FET with gate and drain via connections

A new microwave device format that combines flip-chip mounting and via-connection technologies is described. This approach avoids many of the compromises that are inherent in conventional microwave monolithic circuits and will be particularly important in power applications. This letter reviews the rationale for this device format and describes a new method of forming via connections through thick semi-insulating substrates using laser drilling. Preliminary discrete GaAs FET's have been fabricated and results have been obtained through 18 GHz. At 12 GHz, an output power of 308 mW, a 28-percent power-added efficiency, and a 4.5-dB gain have been achieved with a 0.6- mm-wide GaAs FET. Efficiencies as high as 31 percent were achieved with these preliminary devices.     

Damage-free reactive ion etching of GaAs FET gate recess

A GaAs reactive ion etching process is described which has good uniformity and causes no significant electrical damage to the underlying substrate. The process is shown to be suitable for forming the gate recess of a GaAs MESFET. FETs fabricated using the process exhibit DC and RF performance similar to equivalent wet etched devices.<>     

High frequency GaAs switched capacitor filter implemented with GaAs insulated gate FET switches

A switched capacitor filter implemented with 5 mu m GaAs IGFET switches and GaAs MESFET operational amplifiers is presented. The circuit is clocked at 25 MHz. By scaling to 1 mu m IGFETs, a switching speed of about 625 MHz should be attainable. Use of GaAs IGFET switches is shown to greatly reduce power consumption and complexity of the circuit. The low frequency switching instability of the GaAs IGFET is shown to be of no consequence in this application.<>     

A novel self-aligned gate process for half-micrometer gate GaAs ICsusing ECR-CVD

A substitutional self-aligned gate MESFET process for the half-micrometer gate GaAs IC that employs techniques of sidewall formation and precise pattern reversal using ECR (electron cyclotron resonance) CVD (chemical vapor deposition) is discussed. A FET with 0.45-μm gate length showed high performance characteristics, such as a maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz. This process has two advantages over conventional substitutional and refractory gate processes. First, it can incorporate an LDD (lightly doped drain) structure. Second, since the photoresist dummy gates are precisely reversed without using reactive ion etching (RIE) at all, the gate length is dependent only on lithography. The process was demonstrated by the preliminary fabrication of a 16 b×16 b multiplier with 50% yield. The process, with high-performance device characteristics, should fine broad applications in both half-micrometer gate level LSIs and analog ICs     

A novel low-power static GaAs MESFET logic gate

A novel GaAs MESFET logic gate is described. The gate uses depletion mode FET's and is a static one. It is about 30% faster and consumes about 30% of the power of the BFL gate. Ring oscillator circuits have been fabricated using one embodiment of the gate. For unity fan-out, an average propagation delay of 58.7 ps with a power dissipation of 18.8 mW has been achieved.     

Studies of aluminum Schottky barrier gate annealing on GaAs FET structures

Controlled annealing experiments on special GaAs FET structures have been used to assess the integrity of Al/nGaAs Schottky barrier gates. Metallurgical properties of the Al/nGaAs interface were analyzed using microspot Auger electron spectroscopy. Results indicate interdiffusion between Al and GaAs at the baseline annealing temperature of 275°C. At this temperature the three terminal static FET parameters were unaffected by the annealing, but the two terminal gate/source static characteristic was somewhat improved over unannealed control FETs. Annealing the Al gate up to 450°C does not appear to be harmful to the gate/source two terminal static characteristic although at this temperature three terminal static FET characteristics are severely degraded. The Al/nGaAs interface is assessed as being both metallurgically and electrically stable when employed in inert ambient environments up to 275°C for 24 hr.     

P-column gate FET

A new structure for a GaAs JFET (P-Column Gate FET) is proposed, employing p-column shaped gates in an active n-layer on a semi-insulating substrate, where the current flows through spaces between the gate columns. It was found that Be ion implantation can produce p-column gates. The FET I-V characteristics are also presented and discussed.     

A new gate structure vertical-GaAs FET

A new vertical-(V-) GaAs FET exhibiting penthode-like characteristics has been developed and realized experimentally by combining reactive ion etching (RIE) and MO-CVD techniques. The unique feature of this device is the use of an insulator/metal/insulator-grating gate embedded in a GaAs single crystal. A comparison of the dc characteristics of the new device with a standard permeable base transistor (PBT) has been carried out. The improved device performance expected from this structure is discussed in detail.     

A 500-MHz 16*16 complex multiplier using self-aligned gate GaAs heterostructure FET technology

A 16*16-bit complex multiplier using self-aligned gate GaAs heterostructure FET technology has been demonstrated. The multiplier uses a modified Booth's algorithm and three stages of pipeline with an embedded accumulator to allow the computation of a complex multiply function. A total of 4500 gates and over 20000 devices are required to implement this function and self-test functions. The chip produces a 20-bit output allowing 40 bits to describe a complex number result. Direct coupled NOR-gate FET logic was used throughout. The complex multiplier operated at a clock rate of 520 MHz with a power dissipation of 4 W under self-test. This corresponds to an average 'loaded' gate delay of 96 ps at 0.89 mW/gate. It also means that the multiplier produces a complex product, generated using four real multiplications and two additions, in less than 8 ns. This result demonstrates the high-speed capability of LSI digital circuits fabricated using MBE-grown GaAs heterostructure FET technology.<>     

功率GaAs FET

本文叙述了目前在研制功率GaAs FET过程中对器件的输出功率有比较重要影响的诸多因素,例如器件的几何结构、源引线寄生电感、热阻、击穿电压等等,以及对这些因素加以克服或限制的技术。折衷的结果将使所研制的器件具有良好的微波性能。     

A functional GaAs FET noise model

It is the purpose of this paper to develop a theory upon which the design of low noise FET amplifiers can be based. This is not a fundamenta model of the noise mechanisms in GaAs FET's, but rather, an endeavor to relate physically measurable device capacitances and resistances to the device noise figure and optimum noise source impedance. I will be shown that the noise performance of an FET can be adequately described by two uncorrelated noise sources. One, at the input of the FET, is the thermal noise generated in the various resis, tances in the gate-source loop. This noise source is frequency dependent and it can be calculated from the equivalent circuit of the FET. The second noise source, in the Output of the FET, is frequency independent, and not recognizably related to any measured parameters. This output nise is a function of drain current and voltage. The decomposition of the FET noise into two uncorrelated sources simplifies the design of broad-band low noise amplifiers. Once the equivalent circuit of a device and its noise figure at one frequency are known, the optimum noise source impedance and noise figure over a broad range of frequencies may be calculated. For the device designer this model also may be helpful in balancing input-output noise tradeoffs.     

A low-distortion K-band GaAs power FET

A K-band low-distortion GaAs power MESFET was developed by incorporating a pulse-type channel doping profile using molecular-beam-epitaxial technology and a novel 0.3-μm T-shaped gate. The low-distortion FETs offer about 10 to 15 dBc improvement in second-harmonic distortion compared to devices fabricated on a uniformity doped active layer. Significantly larger power load-pull contours are obtained with the low-distortion devices, indicating the improved linearity of these devices. In an 8-20-GHz single-stage broad-band amplifier, up to 10 dBc improvement in harmonic performance was achieved using the low-distortion device. This low-distortion device exhibits very linear transconductance as a function of the gate bias. A typical 750-μm-gate-width device is capable of 26 dBm of output power with 6 dB of gain, and power-added efficiency in excess of 35% when measured at 18 GHz. At 25 GHz, the device is capable of 24 dBm of output power with 5 dB associated gain     

A GaAs FET Model for Large-Signal Applications

The use of GaAs FET's under large-signal conditions requires a knowledge of the nonlinear behavior of these devices. A computer program, based on a circuit model with nonlinear elements, has been developed which provides this information. Results from the computer model and examples of its use in microwave circuit design are given.     

GaAs FET RF switches

The device parameter dependences of GaAs FET switch performance have been determined analytically and by two-dimension simulation. FET switch design would maximize the value of the switch quality factor while retaining the power handling capacity. Expressions for both the quality factor and power handling capacity are derived in terms of device parameters, and would enable such optimization to be performed.