一种测量外延层厚度及掺杂浓度的改进方法

在双台面SiGeHBT加工工艺过程中,采用RIE工艺刻蚀发射极台面时,为了避免等离子轰击对外基区表面造成损伤,同时为了防止过刻到基区,必须严格控制发射极台面的高度,从而必须准确知道未刻蚀前的厚度和刻蚀后的厚度。现有的许多对材料厚度及掺杂浓度的分析方法,具有各自的优缺点。本文提出了一种可以同时检测外延层的厚度及掺杂浓度分布的方法,这种方法具有简单、高效、低成本的优点。     

多晶发射极双台面微波功率SiGe HBT

研制成功了可商业化的75mm单片超高真空化学气相淀积锗硅外延设备SGE50 0 ,并生长了器件级SiGeHBT材料.研制了具有优良小电流特性的多晶发射极双台面微波功率SiGeHBT器件,其性能为:β=60 @VCE/IC=9V/ 30 0 μA ,β=1 0 0 @5V/ 50mA ,BVCBO=2 2V ,ft/ fmax=5 4GHz/ 7 7GHz @1 0指,3V/ 1 0mA .多晶发射极可进一步提供直流和射频性能的折衷,该工艺总共只有6步光刻,与CMOS工艺兼容且(因多晶发射极)无需发射极外延层的生长,这些优点使其适合于商业化生产.利用60指和1 2 0指的SiGeHBT制作了微波锗硅功率放大器.60指功放在90 0MHz和3 5V/ 0 2A偏置时在1dB压缩     

InP/InGaAs SHBT器件自对准结构设计和工艺实现

从InP湿法腐蚀各向异性特性实验出发,利用传统的基极-发射极自对准工艺和改进的基极-发射极工艺制作了两种InP/InGaAs SHBT自对准结构,比较了两种自对准工艺对减小基极与发射极台面间距的效果,为制作高频率特性InP/InGaAs SHBT提供了工艺途径.     

InP/InGaAs SHBT器件自对准结构设计和工艺实现

从InP湿法腐蚀各向异性特性实验出发,利用传统的基极-发射极自对准工艺和改进的基极-发射极工艺制作了两种InP/InGaAs SHBT自对准结构,比较了两种自对准工艺对减小基极与发射极台面间距的效果,为制作高频率特性InP/InGaAs SHBT提供了工艺途径.     

InP/InGaAs SHBT器件自对准结构设计和工艺实现

从InP湿法腐蚀各向异性特性实验出发，利用传统的基极-发射极自对准工艺和改进的基极-发射极工艺制作了两种InP/InGaAs SHBT自对准结构，比较了两种自对准工艺对减小基极与发射极台面间距的效果，为制作高频率特性InP/InGaAs SHBT提供了工艺途径.     

SiGe/Si异质结双极晶体管工艺技术研究

介绍了多晶硅发射极双台面SiGe/Si异质结双极晶体管制作工艺流程。通过对LPCVD在n型Si衬底上外延生长SiGe合金层作为异质结双极晶体管基区、自中止腐蚀工艺制作发射区台面、多晶硅n型杂质掺杂工艺制作发射极、PtSi金属硅化物制作器件欧姆接触等工艺技术进行研究,探索出关键工艺的控制方法,并对采用以上工艺技术制作的多晶硅发射极双台面SiGe/Si异质结双极晶体管进行了I-V特性及频率特性测试。结果显示该器件饱和压降小,欧姆接触良好,直流电流放大倍数β随Ic变化不大,截止频率最高达到11.2 GHz。     

高截止频率异质结双极晶体管的研制

本文介绍了研制异质结双极晶体管(HBT)的工艺过程。使用MOCVD生长的GaAlAs/GaAs多层结构外延材料,采用离子注入隔离和湿法腐蚀技术,实现基极与发射极台面自对准工艺,研制出截止频率为22GHz的HBT。     

SiGe/Si HBT低频噪声特性研究

对Si/Si1-xGexHBT的低频噪声进行了模拟。频率、基极电流、集电极电流、发射极几何尺寸(面积、条长)、Ge组份x、温度等诸多因素都对低频噪声有影响。模拟结果表明,Si/SiGeHBT具有优异的低频噪声特性。     

发射极-基极-发射极结构PNP型AlGaAs/GaAs HBT电流增益的理论分析

建立了PNP型异质结双极晶体管基区少数载流子浓度的解析模型。理论分析了发射极－基极－发射极布局的PNP型HBT的电流增益。讨论了不同基极电流成分,如外基区表面复合电流,基极接触处的界面复合电流,基区体内复合电流,以及刻蚀台面处的台面复合电流对电流增益的影响。     

Si/SiGe/SiHBT直流特性的可靠性

对单台面SiGeHBT在E-B结反偏应力下直流特性的可靠性进行了研究。研究结果表明,随应力时间的增加,开启电压增加,直流电流增益下降,特别是在低E-B正偏电压时下降明显;而交流电流增益退化缓慢。     

SiGe HBT发射区台面自中止腐蚀技术研究

台面结构SiGe/Si异质结晶体管制作过程中,发射区台面形成尤为关键。由于干法刻蚀速率难以精确控制,且易损伤SiGe外基区表面,SiGe自中止湿法腐蚀成为台面结构SiGe/Si异质结晶体管制作过程中的优选工艺。分析了SiGe自中止腐蚀的反应机理,对腐蚀条件包括掩蔽膜的选取,温度、超声等因素对腐蚀速率及均匀性的影响进行摸索,取得了较好结果,最终采用该技术完成了SiGe/Si npn型异质结晶体管的制作,测得其电流增益β>80,对采用台面结构制造SiGe/Si HBT具有一定参考价值。     

一种新型双多晶自对准结构的高压功率SiGe HBT

为了改善高压功率SiGe HBT的综合性能,应用图形外延SiGe工艺,研制出了一种新型的双多晶自对准SiGe HBT器件.相对于双台面结构的SiGe HBT而言,该结构的SiGe HBT在发射极总周长不变的情况下,其发射结面积减少超过50%,集电结面积减少近70%,BVCBO也提高了近28%.经测试,器件的结漏电和直流增益等参数均符合设计要求.     

A 30-Gbit/s demultiplexer IC based on Si/SiGe emitter baseheterojunction bipolar transistors

A 30-Gbit/s demultiplexer IC has been fabricated and tested using an improved double mesa Si/SiGe heterojunction bipolar transistor process. This is-to our knowledge-the highest ever reported bit rate for “real” (as opposed to drift transistor) Si/SiGe HBT circuits. The result was mainly reached by scaling down the transistor sizes to reduce parasitics. The minimum emitter mesa width was 1 μm     

多晶发射极双台面微波功率SiGe HBT

研制成功了可商业化的75mm单片超高真空化学气相淀积锗硅外延设备SGE500,并生长了器件级SiGe HBT材料.研制了具有优良小电流特性的多晶发射极双台面微波功率SiGe HBT器件,其性能为:β=60@VCE/IC=9V/300μA,β=100@5V/50mA,BVCBO=22V,ft/fmax=5.4GHz/7.7GHz@10指,3V/10mA.多晶发射极可进一步提供直流和射频性能的折衷,该工艺总共只有6步光刻,与CMOS工艺兼容且(因多晶发射极)无需发射极外延层的生长,这些优点使其适合于商业化生产.利用60指和120指的SiGe HBT制作了微波锗硅功率放大器.60指功放在900MHz和3.5V/0.2A偏置时在1dB压缩点给出P1dB/Gp/PAE＝22dBm/11dB/26.1%.120指功放900MHz工作时给出了Pout/Gp/PAE＝33.3dBm (2.1W)/10.3dB/33.9%@11V/0.52A.     

16 Gbit/s multiplexer IC using double mesa Si/SiGe heterojunction bipolar transistors

A double mesa Si/SiGe heterojunction bipolar transistor (HBT) was developed for application in integrated circuits. The HBT is characterised by an emitter base heterojunction and consequently by a high base doping concentration. By using these transistors an integrated digital circuit, a multiplexer, was implemented. The measured bit rate of this first Si/SiGe HBT circuit was 16 Gbit/s.<>     

A robust all-wet-etching process for mesa formation of InGaAs-InP HBT featuring high uniformity and high reproducibility

A simple InP-based heterojunction bipolar transistors (HBT) fabrication process featuring high uniformity and high reproducibility is introduced. No dry etching method was utilized for triple-mesa formation to avoid plasma damage to the device surface. An all-wet etching method was specially developed. This process is relatively simple compared to the conventional HBT fabrication process with respect to the emitter mesa formation by one-step selective etching. Uniformity of the current gain over a 3-in diameter wafer was approximately 2.9%, and the variation of the current gain of 17 wafers was 2.9 (max.-min.). The current gain cutoff frequency and the maximum oscillation frequency were 145 and 174 GHz, respectively. The mean time to failure was over 5 /spl times/ 10/sup 6/ h at 150/spl deg/ C whose criterion was over 3% changes in the current gain. This process is suitable for mass production of ultrahigh speed ICs in high yield.     

用离子注入和掩埋金属自对准技术改善Si/SiGe HBT性能

在器件纵向结构确定后,常规工艺制作的SiGe／SiHBT噪声性能不理想的主要原因是其基极电阻较大,高频性能不理想主要是由于其基极和发射极台面面积较大造成的;为达到改善其高频与低噪声性能的目的,在不改变光刻工艺精度的情况下,采用离子注入和掩埋金属自对准工艺方法完成了器件制作;与传统制作方法相比,前者可减小外基区电阻,后者可以减小电极接触电阻,并能使器件的台面面积做得更小。在此基础上,我们测试了器件的最小噪声系数与最高截止频率,结果表明：用自对准工艺制作的器件的高频噪声与频率性能都显著改善。     

GaN HBT: toward an RF device

This paper reviews efforts to develop growth and fabrication technology for the GaN HBT. Conventional devices are grown by plasma assisted MBE on MOCVD GaN templates on sapphire. HBTs were fabricated on LEO material identifying threading dislocations as the primary source of collector-emitter leakage which was reduced by four orders of magnitude for devices on nondislocated material. Base doping studies show that the mechanism of this leakage is localized punch-through caused by compensation near the dislocation. High contact and lateral resistance in the base cause large parasitic common emitter offset voltages (from 1 to 5 V) in GaN HBTs. The effect of this voltage drop on common emitter characteristics is discussed. The combination of this voltage drop and the emitter collector leakage make Gummel and common base characteristics unreliable without verification with common emitter characteristics. The selectively regrown emitter bipolar transistor is presented with a DC current gain of 6 and early voltage greater than 400 V. The transistor operated to voltages over 70 V. This device design reduces base contact resistance, and circumvented difficulties associated with the emitter mesa etch process. The Mg memory effect in MOCVD grown GaN HBTs is discussed, and MBE grown device layers are shown to produce sharp doping profiles. The low current gain of these devices is discussed, and an HBT with a compositionally graded base is presented, as well as simulations predicting further current gain improvements with base grading     

High-speed scaled-down self-aligned SEG SiGe HBTs

A scaled-down self-aligned selective-epitaxial-growth (SEG) SiGe HBT, structurally optimized for an emitter scaled down toward 100 nm, was developed. This SiGe HBT features a funnel-shaped emitter electrode and a narrow separation between the emitter and base electrodes. The first feature is effective for suppressing the increase of the emitter resistance, while the second one reduces the base resistance of the scaled-down emitter. The good current-voltage performance - a current gain of 500 for the SiGe HBT with an emitter area of 0.11 /spl times/ 0.34 /spl mu/m and V/sub BE/ standard deviation of less than 0.8 mV for emitter width down to about 0.13 /spl mu/m - demonstrates the applicability of this SiGe HBT with a narrow emitter. This SiGe HBT demonstrated high-speed operation: an emitter-coupled logic (ECL) gate delay of 4.8 ps and a maximum operating frequency of 81 GHz for a static frequency divider.