A new configuration of CCD imager with a very low smear level

In this paper a new configuration of CCD image sensor is proposed to improve smear. This new sensor introduces a storage region, with a selective gate and drain section, between the imaging region and a readout register. The configuration and operating principles of the new device are described. Preliminary experimental results with a 402(H) × 502(V) element image sensor are also reported. The introduction of the storage region is confirmed to be strikingly efficient in lowering the smear level.     

A new configuration of CCD imager with a very low smear level—FIT-CCD imager

A new configuration of CCD imager has been developed to improve smearing. This new sensor introduces a storage region, which consists of pairs of vertical BCCD registers, between an interline transfer CCD imaging region and a readout horizontal CCD register. The configuration and operation of the new device (FIT-CCD imaging device) are described, together with the experimental results for 402(H) times 500(V) element imaging devices. The smear level observed is low as ∼0.45 percent at 50 times the saturation exposure, being the lowest level so far obtained in solid-state imagers. Degradation in the contrast transfer function due to introduction of the storage region is very little because of the minimized vertical transfer loss by the storage region configuration with pairs of half-long BCCD registers.     

高帧频低拖尾帧转移CCD驱动技术

帧转移CCD在先进高光谱遥感技术中具有非常重要的应用价值,而拖尾问题是其在高光谱成像等高帧频应用中存在的最大障碍之一。为了减小拖尾的影响,建立了驱动器、PCB传输线及CCD内部结构一体化的驱动信号传输模型,比传统模型能更准确地预测CCD内部和外部的驱动信号波形;仿真对比了各种典型参数对CCD驱动信号波形的影响,仿真与实测结果具有很好的一致性。根据仿真结果进行了高帧频帧转移CCD驱动电路的优化设计,实现了100 ns的行转移时间,在500 fps的帧频下获得了拖尾系数小于1%的驱动效果,为进一步提高CCD的工作帧频提供了保障。     

An S-VHS compatible 1/3" color FT-CCD imager with low dark current by surface pinning

A Frame-Transfer CCD imager for consumer applications has been developed with low dark current by using hole accumulation at the entire Si-SiO/sub 2/ interface of the image pixel during integration, called "All-Gates Pinning", or AGP. All sensor features, such as vertical anti-blooming and electronic shutter are maintained. The sensor combines thin polysilicon electrodes with mosaic color filters for increased sensitivity and resolution, and uses minimized capacitances and a double metal technology for increased frame shift frequency to obtain low smear. The image pixel operation and optimization are presented, Measurements show a 30 times lower dark current, and 8 times lower fixed-pattern noise with all-gates pinning compared to a conventional device. A frame shift frequency of 15 MHz is achieved. These new features allow the reduction from 2/3" to 1/3" image format without sacrificing the performance.<>     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

超大电流密度低压二极管研究

论述了低压大电流行业所用整流二极管的超大电流密度、超低功耗设计的重要性.介绍了设计方法、工艺措施及实验结果.分析表明,只要保证基区宽度不大于小电流下的载流子扩散长度,保证足够的表面扩散浓度,就能保证二极管在1000A/cm2的特大电流密度下仍有很低的压降.     

High sensitivity organic photodiodes with low dark currents and increased lifetimes

Organic semiconductors hold the promise for large-area, low-cost image sensors and monolithically integrated photonic microsystems. This requires the availability of photodiodes offering at the same time high quantum efficiency, low noise and long lifetimes. Although published structures of organic photodiodes offer high external quantum efficiencies (EQE) of up to 76% [F. Padinger, R.S. Rittberber, N.S. Sariciftci, Effects of postproduction treatment on plastic solar cells, Advanced Functional Materials 13 (2003) 1, P. Schilinsky, C. Waldauf, C.J. Brabec, Recombination loss analysis in polythiophene based bulk heterojunction photodetectors, Applied Physics Letters 81 (20) (2002) 3885], [1], [2] they normally suffer from short lifetimes of only a few hundred hours as well as large dark currents. In our work the lifetime of a poly(3-hexylthiophene) (P3HT) and [6,6]-phenyl-C61 butyric acid methyl ester (PCBM) heterojunction photodiode structure was increased to several thousand hours by omitting the widely used poly(3,4-ethylenedioxythiophene):poly(styrenesulfonic acid) (PEDOT:PSS) anode layer. In addition, a simple model of optical interference and absorption effects was used to find the optimum thickness that combines high quantum efficiency with low dark current. As a result, we report on organic photodiodes with state-of-the-art EQE of 70% at 0 V bias, an on/off current ratio of 10⁶ at −1 V and 40 mW/cm² illumination, dark current densities below 10 nA/cm² at −1 V, and a lifetime of at least 3000 h.     

CH3NH3PbI3/C60 heterojunction photodetectors with low dark current and high detectivity

CH₃NH₃PbI₃/C₆₀ heterojunction photodetectors were here fabricated. The peak EQE achieves ∼80% in the visible-light range from 400 to 760 nm. Benefitting from eliminating the leakage current (PEDOT:PSS-free), extremely low dark current density (0.6 nA/cm²) and high specific detectivity (2.7 × 10¹³ Jones) are acquired.     

Transparent photodetectors with ultra-low dark current and high photoresponse for near-infrared detection

A remarkable progress in research works regarding flexibility and transparency of organic optoelectronic devices has been observed in the past decade compared to their inorganic counterparts. However, few studies have been devoted to the advancement of a transparent organic photodetector. In this study, we have used a wavelength-selective bulk-heterojunction of ClAlPc:C₆₀ as active layer and Cu:Ag/WO₃ metal alloy as electrode to realize a see-through organic photodetector (OPD) with an average visible transmission of 76.92%. The optimized transparent OPDs show an average dark current density of 0.36 nA cm⁻² and a rise/fall time of <5 μs under a bias voltage of −2 V, which could be potentially applied in a home security system based on invisible near-infrared detection.     

Fabrication of very high resistivity Si with low loss and crosstalk

We have used proton and As⁺ implantation to increase the resistivity of conventional Si (10 Ω-cm) and Si-on-quartz substrates, respectively. A high resistivity of 1.6 MΩ-cm is measured that is close to intrinsic Si and semi-insulating GaAs. Very low loss and cross coupling of 6.3 dB/cm and -79 dB/cm (10 μm gap) at 20 GHz are measured on these samples, respectively. The very high resistivity and improved rf performance are due to the extremely fast ~1 ps carrier lifetime stable even after a 400°C annealing for 1 h. Little negative effect on gate oxide integrity is also observed as evidenced by the comparable stress-induced leakage current and charge-to-breakdown for 30 Å oxides     

Laser-recrystallized polycrystalline-silicon thin-film transistors with low leakage current and high switching ratio

Laser-recrystallized polycrystalline-silicon thin-film transistors (poly-Si TFT's) with offset-gate structures have been fabricated on quartz substrates. Offset-gate structures make it possible to reduce leakage currents to as low as 5 × 10^-14A/µm at VD= 10 V, more than two orders of magnitude lower than that in conventional-structure poly-Si TFT's. Optimization of the dopant concentration in offset-gate regions minimizes degradation of drive current, enabling high switching ratios exceeding 10⁸. Calculations based on the quasi-two-dimensional model indicate that the reduction in leakage current is due to a decrease in lateral electric field strength in the drain depletion region.     

大容量低阻抗耐高纹波电流片式固体钽 电解电容器的进展

介绍了大容量、低阻抗、耐高纹波电流的片式固体钽电解电容器的突出特点, 列举在便携式移动电话、笔记本电脑, 开关电源的ＤＣ／ＤＣ变换器的部分应用实例。这类电容器的应用十分引人关注。     

Millimeter-wave folded reflector antennas with high gain, low loss, and low profile

Periodic and quasi-periodic structures, printed on a dielectric substrate, can be employed to control the reflection and transmission properties of incident waves as a function of structure geometry. Local variations of the element geometry on a substrate with backside metallization - resulting in respective variations of the reflection phase angle - can be used to design printed reflectarray antennas. The dual-polarization properties of such antennas, together with polarizing grids or slot arrays, can be exploited for the realization of compact, low-profile folded reflector antennas. Examples of some antennas of this type are presented, covering the 60 GHz range for communication and ISM applications, and 76 to 77 GHz for automotive radars.     

Poly-Si gate electrodes for AlGaN/GaN HEMT with high reliability and low gate leakage current

AlGaN/GaN HEMT with a BF₂-implanted polycrystalline Si gate has been characterized through comparison to TiN gate electrodes. Positive threshold voltage (V_th) shift was observed with the addition of F ions, which in turn degraded the effective electron mobility (μ_eff) by diffusion into the AlGaN/GaN interface and GaN layer. A large reduction in gate leakage current (J_g) was achieved and the property was maintained even after strong reverse-bias stressing. No additional degradation in μ_eff was observed, suggesting the formation of a stable poly-Si/AlGaN interface. Therefore, poly-Si gate electrodes have advantages in reducing the J_g and robustness against reverse-bias stressing.     

InGaAsP/InGaAs heterojunction p-i-n detectors with low dark current and small capacitance for 1.3?1.6 ?m fibre optic systems

A new long wavelength p-i-n photodetector, consisting of an In0.53 Ga0.47 As absorbing layer and an adjacent InGaAsP p-n junction is demonstrated. These diodes exhibit dark currents as low as 0.2 nA and a capacitance < 0.5 pF at ? 10 V for a device area of 1.3 × 10?4 cm2. The external quantum efficiency is ? 60% at ? = 1.3 ?m for front illumination. A systematic study of the background doping of the quaternary layers using different InP sources is also reported.     

A low power and high speed data transfer scheme with asynchronouscompressed pulse width modulation for AS-Memory

This paper describes an approach to a low power and high speed data transfer scheme in the internal data bus of an AS-Memory which has ASIC circuitry and memory array. Pulse width modulation, which is operated asynchronously, is applied to the wide internal data bus. An automatic gain controlled amplifier which amplifies many small signals from the memory array is also newly developed to achieve a fast data output. Applying this architecture to an AS-Memory, the area and power consumption of the internal data bus interface can be reduced to 25% and 36%, respectively     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

A small dipole-fed resonant reflector antenna with high efficiency, low cross polarization, and low sidelobes

The computer-aided optimization of a small five-wavelength diameter reflector antenna with a center-supported dipole-disk feed is described. The primary radiation is controlled by using a patented beamforming ring to give low cross polarization and low sidelobes due to spillover. The efficiency is maximized by controlling and taking advantage of the multiple reflections between the feed and the reflector. This has inspired the name "resonant reflector antenna." The gain from the feed reflector resonances is so large that it compensates almost completely for the about 1 dB loss due to center blockage of the aperture.