High Performance Static Segment On-Chip Memory for Image Processing Applications

The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power and area efficient design without compromising quality in data-intensive computing applications. This paper proposes a design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications. In this static segment method, n-bit data array is reduced by m-bit data array for significant value of input data to achieve balanced design metrics at the cost of accuracy. The proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture for the approximate computing applications. From the overall simulation results, the proposed 4-bit SSOC SP SRAM design provides 49.02% area savings, 50.62% power reduction and 16.92% speed improvement at the cost of 0.64% Peak Signal to Noise Ratio (PSNR) and exhibits same visual quality in comparison with the existing 8-bit conventional on-chip SP SRAM design in the image processing applications.     

一种用于片上静电防护的新型闩锁免疫可控硅

可控硅(SCR)被广泛应用于片上静电放电(ESD)防护。由于SCR的低维持电压特性,闩锁问题一直是其应用于高压工艺ESD防护的主要问题。改进设计了一种新型SCR器件,即MOS High-holding Voltage SCR (MHVSCR)。通过对SCR寄生三极管正反馈进行抑制,并提高维持电压,实现了闩锁免疫。详细分析了MHVSCR提高SCR维持电压的可行性、工作原理以及实现步骤。基于Sentaurus TCAD的仿真结果表明:设计的器件将传统器件的SCR维持电压从2.8 V提高至15.88 V,有效实现了SCR在12 V工艺下的闩锁免疫能力。     

High Speed and Low Energy Capacitively Driven On-Chip Wires

We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8x over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5x. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7x using a 200 mV swing.     

Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection

MOS-triggered silicon-controlled rectifier (SCR) devices have been reported to achieve efficient on-chip electrostatic discharge (ESD) protection in deep-submicrometer CMOS technology. The channel length of the embedded MOS transistor in the MOS-triggered SCR device dominates the trigger mechanism and current distribution to govern the trigger voltage, holding voltage, on resistance, second breakdown current, and ESD robustness of the MOS-triggered SCR device. The embedded MOS transistor in the MOS-triggered SCR device should be optimized to achieve the most efficient ESD protection in advanced CMOS technology. In addition, the layout style of the embedded MOS transistor can be adjusted to improve the MOS-triggered SCR device for ESD protection.     

Multiprocessor,Multithreading and Memory Optimization for On-Chip Multimedia Applications

Multiprocessor System-on-Chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. The techniques for processor design and application optimizations can be combined together for more efficient design of these systems. Thus, the memory optimization techniques improving the data locality can be combined with multithreading technology, improving the overall processor efficiency. The combination of these techniques is mainly challenged by the adaptation of memory optimization techniques to the high parallelism offered by the multithreading environments. This paper presents an in-depth analysis of the impact of multiprocessor and multithreading environments on memory optimization techniques. A discussion is provided on the different types of parallelization (fine and coarse grain) and their influence on memory optimization technique. Some improvements on existing memory optimization techniques are presented as well some adaptation necessary to use them in this type of environment.

一种片上集成低压高精度电流检测电路

提出了一种应用于电流模PWM DC-DC转换器的片上集成电流检测电路.它利用检测电阻和检测晶体管的结合,实现电感电流的检测;同时,在I-V转换电路中,运用结构简单的电流镜连接的共栅放大器实现反馈控制.在10～600 mA电感电流范围内,都可以得到高精度的检测电流,最小检测误差为0.04%.该电路在VTHN=0.735 V、|VTHP|=0.941 V的0.5 μm 1P2M CMOS工艺条件下,电路最低工作电压为1.5 V.     

用于高压ESD防护的高维持电流SCR器件

静电释放(ESD)是指电荷在两个电势不等的物体之间转移的物理现象,它存在于人们日常工作生活的任意环节。随着集成电路特征尺寸不断减小、集成度不断增高,芯片对ESD也变得越来越敏感。为了用尽可能小的版图面积来实现ESD防护,利用晶闸管结构(SCR)来实现集成电路的ESD防护已成为当下的研究热点。但传统SCR的维持电压和维持电流都很低,若直接将其应用于电源ESD防护则会导致严重的闩锁效应(latch-up)。基于高维持电流设计窗口,提出一种可用于15 V电路的抗闩锁SCR器件,并通过混合仿真验证了该器件的有效性。     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

An Integrated Power Supply System for Low Power 3.3 V Electronics Using On-Chip Polymer Electrolyte Membrane (PEM) Fuel Cells

A stabilized power supply realized by chip-integrated micro fuel cells within an extended CMOS process is presented in this paper. The fuel cell system delivers a maximum power output of 450 ? W/cm². The electronic control circuitry consists of an LDO, an on-chip oscillator and a programmable timing network. The core system consumes an average power of 620 nW. The system reaches a current efficiency of up to 92% and provides a constant output voltage of 3.3 V.     

Low Voltage, Low Power and High Performance Current Conveyors for Low Voltage Analog and Mixed Mode Signal Processing Applications

A novel CMOS current conveyor (CC), which can be reconfigured into various types of CCs and is capable of operating at ±1.0 V, is presented. The proposed CC has near rail-to-rail input (–1.0 to 1.0 V) swings and consumes 0.6 mW power. The input current range of the proposed CC is from –0.5 to 0.5 mA. P-Spice simulations confirm the CC performance. The CC has a voltage transfer bandwidth of 100 MHz and current transfer of bandwidth of 200 MHz. Applications of CCs in the design of square rooting and current squaring functions have also been explored.     

一种适用于低ESR应用的高精度RBCOT环路

提出了一种适用于低ESR电容、具有快速瞬态响应和高输出精度的纹波控制COT(RBCOT)实现电路,并利用改进的等效三端开关模型,对包含分压网络的控制环路进行了精确的小信号建模。该环路在保持快速瞬态响应能力的同时,利用SW点的1阶滤波信号来产生虚拟电感电流纹波,避免了次谐波振荡现象。通过谷值采样电路,对滤波信号的谷值进行采样。采样电路在每个开关周期执行刷新操作,并在上电和瞬态变化阶段进行加速充电。纹波叠加电路将增强纹波和谷值采样信号精确地叠加到反馈电压端,保证电路输出精度较高。采用0.35μm 18 V BCD工艺,对纹波控制COT控制环路进行仿真。结果表明,在4.5~18 V输入电压范围内,输出电压的失调在1 mV范围以内,控制环路可以对瞬态变化进行快速调整。     

低压应用的高性能甚高频功率VDMOSFETs

采用梯形栅结构和难熔金属钼栅工艺 ,研制出了高性能 ,低电压工作 ,适用于移动通信的甚高频功率VDMOS场效应晶体管 .该器件在 175 MHz、 12 V低电压工作条件下 ,输出功率为 12 W,漏极效率为 70 % ,功率增益为 12 d B     

低压应用的高性能甚高频功率VDMOSFETs

采用梯形栅结构和难熔金属钼栅工艺,研制出了高性能,低电压工作,适用于移动通信的甚高频功率VDMOS场效应晶体管．该器件在175MHz、12V低电压工作条件下,输出功率为12W,漏极效率为70%,功率增益为12dB．     

CPU中可伸缩低开销的硬件调试器设计

介绍了一种基于JTAG的片上调试的低开销、可伸缩、支持“非侵入性”调试的硬件实现方法。该实现方法是通过在片上调试模块中引入一组映像寄存器，用于跟踪和设置CPU的状态。使用该方法避免了在CPU的关键路径上插入扫描链而限制了CPU性能提高的缺点。此外，本文还阐述了精确硬件断点的实现方法，调试模块实时监视数据地址总线和指令地址总线，当地址与预设值吻合时使CPU进入调试模式，该实现方法支持在程序全速运行时在断点处进入调试模式。本文所提出的方法已经在CK520嵌入式CPU中得到应用和证明。     

High Speed On-Chip Signal Generation for Debug and Diagnosis

This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma–delta modulation in the digital amplitude-domain and converted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed prototype implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semiconductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4?GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-for-test (DFT), or built-in self-test (BIST).     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机. 这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps. 基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路. 该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片,所测的接收机性能如下：噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV. 该接收机采用1.8V电源电压,I, Q两路消耗的总电流为44mA.     

Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.     

Synchronous Branch Guide Directional Couplers for Low and High Power Applications

Branch-guide directional couplers can be built in most types of transmission line. A design procedure is here developed which gives predictable and superior performance over a specified frequency band. A new chart was constructed from which the coupler impedances or admittances can be calculated quickly and with sufficient accuracy for nearly all practical applications. A five-branch, 6-db coupler and a thirteen-branch, 0-db coupler were constructed in waveguide. The measured points and computed curves were in excellent agreement. Over the frequency band of 1300 /spl plusmn/ 130 Mc, the 0-db coupler had a VSWR of less than 1.07, its insertion loss was better than 0.05 db, and the couplings into the two remaining arms were weaker than 20 db. This coupler can pass at least 5 Mw of peak power in air at atmospheric pressure.     

用于射频SOC芯片的低噪声高电源抑制比LDO

设计了一种能够为射频芯片提供低噪声、高PSRR、全集成LDO.采用SMIC 0.18μmRF工艺实现,芯片有效面积0.11 mm2.测试结果表明:当输出电流从0跳变为20 mA时,最大Ripple 为100 mV,稳定时间2μs;当输出电流为20mA,频率到1 MHz的情况下,PSRR＜-30 dB;从1～100 kH...     

CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-$mu$m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.