基于二极管技术优化射频集成电路的ESD

在CMOS集成电路设计中,工艺尺寸不断减小、栅氧厚度不断变薄,对ESD提出更高的要求。尤其在射频集成电路中,ESD的寄生电容对射频性能将产生不可忽略的影响。基于二极管正向偏置对ESD电流的泄放能力,通过引入电感和电容对ESD脉冲的精确模拟,通过设计有效的有源RC电源钳位电路,考虑到版图电阻电容寄生对ESD的射频性能的影响,提出3种版图设计,对各种版图进行了仿真,分析ESD和射频性能,提出了最优的版图,满足射频集成电路应用的ESD保护电路。     

应用于无线收发机前端的片上螺旋型电感的研究

这篇文章探讨了在现在的标准工艺条件下片上集成电感的设计和分析问题,包括片上螺旋型电感的有关版图、损耗机制、模型和参数提取问题,最后以一种被学术界广泛接受的模拟工具对电感的有关设计进行了模拟,给出了模拟结果,并进行了分析,给出了设计片上电感应遵循的原则.随着工艺技术和人们对电感的寄生效应的认识的加深,可以相信片上集成电感在高频电路中的应用将越来越广泛.     

应用于无线收发机关端的片上螺旋型电感的研究

这篇文章探讨了在现在的标准工艺条件下集成电感的设计和分析问题,包括片上螺旋型电感的有关版图,损耗机制,模型和参数提取问题,最后以一种被学术界广泛妆受的模拟工具对电感的有关设计进行了模拟,给出了模拟结果,并进行了分析,给出了设计片上电感应遵循的原,有着工艺技术和人们对电感的寄生效应的认识的加深,可以相信片上集成电感在高频电路中的应用将越来越广泛。     

基于SOI衬底的射频电感优化设计

比较了SOI RF电感与体硅电感的性能,并根据模拟结果分析了电感中空面积,电感形状结构,金属宽度、间距对SOI电感品质因数Q、自谐振频率、电感量L的影响,最后提出了一种基于SOI衬底RF电感的优化设计原则.以往射频集成电感性能的比较并不固定电感值,而文中全部参数的变化都是在电感值相同的情况下进行比较.     

基于SOI衬底的射频电感优化设计

比较了SOIRF电感与体硅电感的性能 ,并根据模拟结果分析了电感中空面积 ,电感形状结构 ,金属宽度、间距对SOI电感品质因数Q、自谐振频率、电感量L的影响 ,最后提出了一种基于SOI衬底RF电感的优化设计原则 .以往射频集成电感性能的比较并不固定电感值 ,而文中全部参数的变化都是在电感值相同的情况下进行比较     

RF平面螺旋微电感计算机模拟研究

应用Greenhouse法对RF平面螺旋微电感进行了计算机模拟,探明了微电感品质因数Q值在高频域内的变化规律,得出了微电感金属层厚度、线宽、线间距及线圈数与RF平面螺旋微电感Q值的对应关系。研究发现,RF平面螺旋微电感的Q值在高频域内随频率增加而呈现先升高后下降的趋势,Q值存在峰值;微电感Q值在某一频率范围内随微电感金属层厚度、线宽的增加而增大;随线间距的增加,微电感的低频性能下降而高频(>1GHz)性能升高;当微电感直径一定时,随线圈数的增加,Q值有下降的趋势。     

硅衬底上射频集成电感研究

在分析硅衬底上射频螺旋电感物理模型的基础上,从几何参数、工艺参数及电感组成形式考虑,用模拟软件ASITIC(Analysis and Simulation of Spiral Inductors and Transformers for Ics)对影响电感值和Q值及谐振频率的各参数进行全面详尽的模拟,得出了几条实用的设计原则且用此模拟方法与所得结论均可有效地指导射频集成电路中集成电感的设计。     

低失配CMOS差分放大器的后端版图设计研究

器件尺寸的缩小提高了晶体管的原始速度,但是集成电路不同模块间有害的相互干扰和版图的非理想性都限制了系统的工作速度和精度。理想的差分放大器电路参数是完全对称的,但实际电路中,由于制造工艺每道工序的不确定性,标称相同的器件都存在有限的不匹配。本文在设计差分电路的版图时通过讨论制造工艺和版图结构对电路性能的影响,设计了失配较小,寄生效应小的单管版图结构,并在全局布局时充分考虑了对称性对电路性能的影响得到了比较理想的差分放大器版图。     

一种C波段E类GaN MMIC功率放大器设计

基于0.25μm GaN HEMT设计了一种工作于C波段、结构简单、宽带高效的E类功率放大器。针对单片微波集成电路(MMIC)功率放大器设计中射频扼流圈所占面积较大且难以实现的问题,采用有限元直流馈电电感替代扼流圈电感,抑制晶体管寄生参数C_ds对最高工作频率的影响,并采用低Q值混合参数匹配网络,将功率放大器电路输入输出的最佳阻抗匹配到标准阻抗50Ω。版图后仿真结果表明,在4.1～4.9 GHz工作频段内,功率附加效率为51.309%～58.050%,平均增益大于11 dB,输出功率大于41 dBm。版图尺寸为2.7 mm×1.4 mm。     

硅集成电感元件的分析、设计与优化

利用采用FDTD(finite-difference time-domain method)方法的计算软件ISE-EMLAB对片上集成电感进行了模拟,并分析了电感的金属宽度、金属间隔、线圈外直径、线圈匝数等设计参数对电感的品质因数、电感值、电阻值等参数的频率特性的影响,进而提出了一种应用于片上集成电感的优化设计的方法.     

A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC's.     

A New Method for Optimizing Layout Parameter of an Integrated On-Chip Inductor in CMOS RF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on-chip integrated inductor, a concise method to increase the Q factor has been ob tained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5 % compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC's.     

金属线宽及线间距渐变的射频螺旋电感

为减少射频螺旋电感的金属导体损耗,提出了一种电感金属线宽及金属间距从外到内逐渐变小的新颖结构.与传统的固定金属线宽和间距的电感相比,该渐变结构电感涡流效应的影响较小,金属导体损耗减小,从而降低其串联电阻,品质因子Q值提高.实验结果确证了所提方法的正确性.对一个高阻硅衬底上6nH电感,优化设计的渐变结构电感Q值在2.46GHz处可达到14.25,比版图面积相同、固定线宽及间距的传统电感高11.3%.因此,在无线通信系统的射频前端,采用这种电感与射频集成电路结合,能获得更好的射频电路性能.     

Performance Analysis of RF Spiral Inductor with Gradually Changed Metal Width and Space

To decrease the metal losses of RF spiral inductor,a novel layout structure with gradually reduced metal line width and space from outside to inside is presented.This gradual changed inductor has less eddy-current effect than the conventional inductor of fixed metal width and space.So the series resistance can be reduced and the quality (Q) factor of the inductor relating to metal losses is increased.The obtained experimental results corroborate the validity of the proposed method.For a 6nH inductor on high-resistivity silicon at 2.46GHz,Q factor of 14.25 is 11.3% higher than the conventional inductor with the same layout size.This inductor can be integrated with radio frequency integrated circuits to gain better performance in RF front end of a wireless communication system.     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

Nonlinear characteristics of on-chip spiral inductors under high RF power

This paper explores silicon CMOS on-chip spiral inductors performance degradation under high RF power. A novel methodology to calibrate and characterize on-chip spiral inductor with large signal inputs (high/medium power) is presented. Experiments showed 12% degradation of quality factor in a particular inductor design when 34 dBm RF power was applied. The degradation of quality factor of inductor can be attributed to a local self heating effect. Thermal imaging of such an inductor under high RF power validates the hypothesis.     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.     

RF operation of MOSFETs under integrated inductors

This paper presents an in-depth analysis of the operation of a CMOS single-chip three-dimensional inductor over a MOSFET structure at RF frequencies. Active circuitry is placed underneath the integrated inductors in order to take advantage of the vacant space. Measurements indicate that the operation of the MOSFET and of the inductor is affected in a predictable manner. The paper theoretically investigates the interaction between the two elements,analyzes the origin of all appearing effects and compares the theory with the experimental data from a typical CMOS process. Moreover, this study proposes possible applications and design guides and confirms the attractiveness of the inductor over MOSFET placement.     

Advanced CMOS technology portfolio for RF IC applications

A high quality 90-nm CMOS-based technology portfolio suitable for various RF IC applications is presented. The portfolio is built up by a wide selection of active and passive components and a user-friendly process design kit (PDK). Layout-optimized RF components are studied in details including state-of-the-art 90 nm RFMOS devices with 120-160 GHz f/sub T/ and very low noise figures, varactors with tradeoff between quality factor and tuning ratio, precision capacitors with metal-insulator-metal and metal-over-metal schemes, and a variety of inductor structures suitable for different RF designs. The effectiveness for isolating substrate RF noise is also compared among several layout schemes. Finally the guidelines and requirements for constructing a useful PDK are addressed.     

Improvement of the quality factor of RF integrated inductors bylayout optimization

A systematic method to improve the quality (Q) factor of RF integrated inductors is presented in this paper. The proposed method is based on the layout optimization to minimize the series resistance of the inductor coil, taking into account both ohmic losses, due to conduction currents, and magnetically induced losses, due to eddy currents. The technique is particularly useful when applied to inductors in which the fabrication process includes integration substrate removal. However, it is also applicable to inductors on low-loss substrates. The method optimizes the width of the metal strip for each turn of the inductor coil, leading to a variable strip-width layout. The optimization procedure has been successfully applied to the design of square spiral inductors in a silicon-based multichip-module technology, complemented with silicon micromachining postprocessing. The obtained experimental results corroborate the validity of the proposed method. A Q factor of about 17 have been obtained for a 35-nH inductor at 1.5 GHz, with Q values higher than 40 predicted for a 20-nH inductor working at 3.5 GHz. The latter is up to a 60% better than the best results for a single strip-width inductor working at the same frequency