Spatially modulated light detector in CMOS with sense-amplifierreceiver operating at 180 Mb/s for optical data link applications andparallel optical interconnects between chips

We present a first realization of a detector receiver combination based on the spatially modulated light detector (SML-detector). The SML-detector gives an output signal that has a shorter falling edge than that of a conventional CMOS detector. It is combined with a sense-amplifier in a standard 0.8-μm CMOS technology, allowing one to receive over 155-Mb/s of light pulses at 5.6-μW average light input power for λ=860 nm. The detector 3-dB bit-rate is 300 Mb/s for this wavelength and for the used spatial topology. For λ=635 nm the detector 3-dB bitrate is 510 Mb/s. Apart from monolithic integration of detector and receiver, further signal processing circuitry (including digital signal processing functions) can be integrated on the same chip. The compact system allows conceiving low cost densely packed optoelectronic receivers for parallel optical interconnects and for wavelength division multiplexing applications in the visible and the near-infrared wavelength range     

Hybrid integration of smart pixels by using polyimide bonding:demonstration of a GaAs p-i-n photodiode/CMOS receiver

The fabrication procedure of smart pixels based on a hybrid integration of compound semiconductor photonic devices with silicon CMOS circuits is described. According to the 0.8-μm design rule, CMOS receiver/transmitter circuits are designed for use in vertical-cavity surface-emitting laser (VCSEL)-based smart pixels, and 16×16 and 2×2 Banyan-switch smart-pixel chips are also designed. By using our polyimide bonding technique, we integrated GaAs pin-photodiodes hybridly on the CMOS circuits. The photodetector (PD)/CMOS hybrid receiver operated error free at up to 800 Mb/s. Successful optical/optical (O/O) operation (a bit rate up to 311 Mbit/s) of the 2×2 Banyan-switch smart-pixel chip implemented with another VCSEL chip is also demonstrated     

High-density digital free-space photonic-switching fabrics usingexciton absorption reflection-switch (EARS) arrays and microbeam opticalinterconnections

We describe a compact digital free-space photonic-switching module that uses microbeam optical interconnections based on stacked planar optics and exciton absorption reflection-switch (EARS) arrays. Microbeam optical interconnections become increasingly attractive as the number of optical input and output (I/O) ports increases because of their small size. The EARS device provides the digital-signal regeneration needed for constructing a multistage switching network. This paper mainly describes the experimental investigation of a prototype switch having a two-stage, 16-input, 16-output structure (four sets of 4×4 switches), with highly dense two-dimensional fiber array pigtails acting as high-density optical I/Os. The prototype is approximately 30×90×22 mm [60 cc]. A relay lens array inserted between stages eliminates the beam spreading caused by diffraction, which decreases the required positioning accuracy for the optomechanical packaging. Two-stage switching at a data transmission rate of 4 Mb/s has been demonstrated. Increasing the operating speed of the switch and introducing an easy assembly method to reduce assembly costs are future enhancements     

Hybrid integration of VCSEL's to CMOS integrated circuits

Three hybrid integration techniques for bonding vertical-cavity surface-emitting lasers (VCSELs) to CMOS integrated circuit chips have been developed and compared in order to determine the optimum method of fabricating VCSEL based smart pixels for optical interconnects and free-space optical processing. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuit and making electrical contacts to the n- and p-mirrors. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. The 4×4 and/or 8×8 arrays of bonded VCSELs produced electrical and optical characteristics typical of unbonded VCSELs. Threshold voltages down to 1.5 V and dynamic resistance as low as 30 Ω were measured, indicating good electrical contact was obtained. Optical power as high as ~10 mW for a VCSEL with a 20-μm aperture and 0.7 mW with a 6-μm aperture were observed. The VCSELs were operated at 200 Mb/s (our equipment limit) with the rise and fall times of the optical output <1 nS     

Realization and characterization of 8×8 resonant cavity LEDarrays mounted onto CMOS drivers for POF-based interchipinterconnections

An 8×8 array of resonant-cavity light emitting diodes (RCLED's) emitting at 980 nm and flip-chip mounted onto complimentary metal-oxide-semiconductor (CMOS) integrated drivers, is presented. The RCLED's are optimized for maximal extraction efficiency into the numerical aperture of polymer optical fibers (NA=0.5) and minimal optical crosstalk. Design of the optimal cavity structure is presented, and 8×8 arrays are realized and mounted directly onto standard CMOS chips using a solder reflow technique. The CMOS integrated drivers are designed for high-speed operation and low-power consumption, and are realized in 0.8 and 0.6-μm CMOS technology. The electrooptical modules have been realized and characterized, and over 50-μW optical power coupled to POF at 3-mA drive current is reported. Open eye diagrams at operation speed up to 250 Mb/s are presented. These characteristics are compatible with CMOS integrated low-power receivers     

Scaling optoelectronic-VLSI circuits into the 21st century: atechnology roadmap

Technologies now exist for implementing dense surface-normal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAs-AlGaAs multiple-quantum-well p-i-n diodes for on-chip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic transceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of future CMOS technology     

Design and analysis of single-mode oxidized VCSELs for high-speedoptical interconnects

Oxide-confined vertical-cavity surface-emitting laser diodes (VCSELs) are fabricated for applications in high-performance optical interconnects. Both 980-nm as well as 850-nm wavelength devices in one- and two-dimensional arrays are investigated. Noise properties of single- and multimode devices under different operation conditions are relative intensity noise of single-mode devices can be as low as -150 dB/Hz at output powers of about 1 mW and feedback levels up to -30 dB. Data rates up to 12.5 Gb/s with bit error rates below 10^-11 are achieved with VCSELs showing stable single-mode emission at large-signal modulation, combined with modulation bandwidths exceeding 10 GHz. Arrays with 4×8 elements flip-chip mounted on Si CMOS driver chips ready for use in parallel data transmission systems are presented     

1.3-μm InP-InGaAsP lasers fabricated on Si substrates by waferbonding

1.3-μm InP-InGaAsP lasers have been successfully fabricated on Si substrates by wafer bonding. InP-InGaAsP thin epitaxial films are prepared by selective etching of InP substrates and then bonded to Si wafers, after which the laser structures are fabricated on the bonded thin films. The bonding temperature has been optimized to be 400°C by considering bonding strength, quality of the bonded crystal, and compatibility with device processes. Room-temperature continuous-wave (RT CW) operation has been achieved for 6-μm-wide mesa lasers with a threshold current of 39 mA, which is identical to that of conventional lasers on InP substrates. Additionally, the lasers fabricated on Si have exhibited higher output powers than the lasers on InP, which is due to higher thermal conductivity of Si substrates. From these results, the wafer bonding is thought to be a promising technique to integrate optical devices on Si and implement optical interconnections between Si LSI chips     

Integrated transceivers for optical wireless communications

Line-of-sight free-space optical links can provide extremely high bandwidth communications, but this usually requires that transmitter and receiver are precisely aligned. In order to allow terminals to be mobile, links must be able to track users within their field of view so that the link is maintained. There are various means to do this, but all require complex subsystems with a number of different optical, optoelectronic, and electrical components. A solid-state tracking architecture is introduced and a seven-channel tracking system demonstration described. The system is designed to operate at 155 Mb/s and is, to the best of our knowledge, the first that uses an integrated approach. Arrays of novel resonant cavity LED (RCLED) emitters that operate at 980 nm are used as sources. These are flip-chip bonded to arrays of CMOS driver circuits and integrated with the necessary transmitter optics. The receiver uses a back-illuminated detector array flip-chip bonded to arrays of custom CMOS receivers. All these components are custom and have performance substantially better than nonoptimized commercially available components. In the paper, the design and fabrication of the optics, optoelectronics, and electronics required for this is described. Successful operation of all the subsystems is detailed, together with results from an initial link demonstration.     

Electrooptic planar deflector switches with thin-film PLZT active elements

First prototypes of electrooptic (EO) planar deflector switches (PDSs) are fabricated with hybrid integration on Si substrates. Planar optical modules, made in silica-on-silicon technology, consist of input and output (I/O) waveguide microlenses facing each other and slab waveguides in between. The modules interconnect the I/O fibers with laterally collimated light beams less than 400 /spl mu/m in width at distances up to 100 mm with losses lower than 3 dB. Thin lead lanthanum zirconium titanate (PLZT) films with prism-shaped electrodes grown on SrTiO/sub 3/ substrates form the deflector elements. The PLZT films are more than 10 /spl mu/m thick with EO coefficients about 40 pm/V. The deflector assembly technology provides chip vertical positioning accuracy better than 1 /spl mu/m. The deflector chips are attached to the optical substrates with thermo-compression flip-chip bonding. The optical power losses of the modules with test silica chips can be as low as 3.6 dB. However, the lowest module losses achieved with PLZT are about 10 dB. The channel-to-channel switching operations are demonstrated at about 40 V and switching times less than 500 ns.     

Smart pixel optoelectronic receiver based on a charge sensitiveamplifier design

The application of charge sensitive amplifier techniques to the design of receivers within smart pixel optoelectronic systems is presented. An example optical input amplifier is given which should provide high sensitivity (±0.3 μA differential), low power consumption (0.6 mW) and small area usage (50 μm×20 μm) for operation at a conventional CMOS bit rate of 100 Mb/s. The minimum (simulated) optical switching energy is 6 fJ     

Smart CMOS focal plane arrays: a Si CMOS detector array andsigma-delta analog-to-digital converter imaging system

This paper evaluates the potential for the real-time utilization of high frame rate image sequences using a fully parallel readout system. Multiple readout architectures for high frame rate imaging are compared. The application domain for a fully parallel readout system is identified, and the design for a fully parallel, monolithically integrated smart CMOS focal plane array is presented. This focal plane image processing chip, with an 8×8 array of Si CMOS detectors each of which have a dedicated on-chip current input first-order sigma-delta analog-to-digital converter front end, has been fabricated, and test results for uniformity and linearity are presented     

An output buffer for 5 V applications in a 0.18 μm 1.8 V/3.3 V CMOS process

Abstract

This article presents a novel output buffer it realized with low-voltage (1.8- and 3.3-V) transistors to transmit high-voltage signals for 5-V applications. Otherway, the proposed circuit also can apply to transmitting higher voltage signals using lower voltage process integrated circuit. The buffer converts 0/1.8-V voltage swing to 0/5-V voltage swing by three steps. The simulation shows the buffer has good AC/DC characteristics. The proposed buffer has been fabricated in a 0.18-μm 1.8/3.3-V 1P6M CMOS process. The experimental results have confirmed that the proposed buffer can be successfully operated without suffering high-voltage gate-oxide overstress in the 5-V interface. In addition, a new level converter that can convert 0/3.3-V voltage swing to 1.8/5-V voltage swing is also presented in this article. The proposed level converter is realized with only 3.3-V transistors. The experimental results have also confirmed that the proposed level converter can be operated correctly.     

高精度采集控制器的设计

该控制器采用24位高精度串行A/D转换器CS5524,极大地提高了数据采集的精度,简便的三线串行输出模式节省了89C52的接口资源.LM19264液晶显示模块,实现了实时显示采集数据和运行曲线的功能;人机界面的操作采用按键输入的方式,实现了方便的菜单操作;另外,使用USB1.1通信方式,通讯速率为1Mb/s,实现了与P...     

High-speed optoelectronic VLSI switching chip with >4000 opticalI/O based on flip-chip bonding of MQW modulators and detectors tosilicon CMOS

We present the first high-speed optoelectronic very large scale integrated circuit (VLSI) switching chip using III-V optical modulators and detectors flip-chip bonded to silicon CMOS. The circuit, which consists of an array of 16×1 switching nodes, has 4096 optical detectors and 256 optical modulators and over 140K transistors. All but two of the 4352 multiple-quantum-well diodes generate photocurrent in response to light. Switching nodes have been tested at data rates above 400 Mb/s per channel, the delay variation across the chip is less than ±400 ps, and crosstalk from neighboring nodes is more than 45 dB below the desired signal. This circuit demonstrates the ability of this hybrid device technology to provide large numbers of high-speed optical I/O with complex electrical circuitry     

A wireless implantable multichannel microstimulating system-on-a-chip with modular architecture.

A 64-site wireless current microstimulator chip (Interestim-2B) and a prototype implant based on the same chip have been developed for neural prosthetic applications. Modular standalone architecture allows up to 32 chips to be individually addressed and operated in parallel to drive up to 2048 stimulating sites. The only off-chip components are a receiver inductive-capacitive (LC) tank, a capacitive low-pass filter for ripple rejection, and arrays of microelectrodes for interfacing with the neural tissue. The implant receives inductive power up to 50 mW and data at 2.5 Mb/s from a frequency shift keyed (FSK) 5/10 MHZ carrier to generate up to 65,800 stimulus pulses/s. Each Interestim-2B chip contains 16 current drivers with 270 microA full-scale current, 5-bit (32-steps) digital-to-analog converter (DAC) resolution, 100 M omega output impedance, and a voltage compliance that extends within 150 and 250 mV of the 5 V supply and ground rails, respectively. It can generate any arbitrary current waveform and supports a variety of monopolar and bipolar stimulation protocols. A common analog line provides access to each site potential, and exhausts residual stimulus charges for charge balancing. The chip has site potential measurement and in situ site impedance measurement capabilities, which help its users indicate defective sites or characteristic shifts in chronic stimulations. Interestim-2B chip is fabricated in the AMI 1.5 microm standard complementary metal-oxide-semiconductor (CMOS) process and measures 4.6 x 4.6 x 0.5 mm. The prototype implant size including test connectors is 19 x 14 x 6 mm, which can be shrunk down to < 0.5 CC. This paper also summarizes some of the in vitro and in vivo experiments performed using the Interestim-2B prototype implant.     

Accurate modeling of monolithic inductors using conformal meshing for reduced computation

Accurate component modeling is a key factor to successful wireline and wireless circuit design in Si/SiGe BiCMOS and RF CMOS. This article presents the application of two planar electromagnetic simulation methods for reducing the memory and computation time requirement for accurate simulation of inductors fabricated with thick analog metal layers. First, a conformal subsectioning technique is briefly discussed in the context of reducing the numerical complexity of octagonal and circular spiral inductor analysis. Second, this article discusses a method for determining if more than a two-sheet model of thick metals is needed for accurate inductor simulation. Finally, the conformal mesh is applied to a 3.3-nH inductor fabricated using the IBM 0.13-/spl mu/m RF CMOS process technology. The simulated and measured results are compared.     

Design and fabrication of a CMOS signal conversion integratedcircuit for remote control hobbyists

The availability of low-cost VLSI (very large scale integration) design software and fabrication services for design, simulation, and layout of integrated circuits has become readily accessible to universities for classroom instruction. The design and fabrication of a CMOS integrated circuit is described, which converts an eight-bit digital signal to a pulse-width modulated (PWM) signal and vice versa for radio control hobbyist transceivers and motor servos. This example design serves to describe a subset of VLSI design tools from the University of California, Berkeley, the University of Washington, and Microelectronics Center of North Carolina and MOSIS fabrication services available for classroom instruction     

High-power laser diodes with dry-etched mirror facets andintegrated monitor photodiodes

High-power broad-area InGaAs-AlGaAs-GaAs single-quantum-well separate-confinement heterostructure (SQW-GRINSCH) lasers with dry-etched mirror facets and integrated monitor photodiodes have been investigated. A multilayer resist system has been employed as a mask for the chemically assisted ion-beam etching (CAIBE) process resulting in vertical and smooth laser facets. Thick electroplated gold layers on top of the ohmic contacts improve the heatsinking of the lasers leading to reasonable continuous-wave (CW) output powers even when the devices are mounted junction-side up. Monolithically integrated monitor photodiodes provide a linear response to the optical output powers of the laser diodes. The properties of broad-area lasers with dry-etched and cleaved facets are almost identical, Record values for the CW output powers of 2.59 W per uncoated facet and wall-plug efficiencies of more than 55% have been achieved with junction-side-down mounted devices     

MSTP光纤传输网的实际应用

分析了某供电局基于SDH光纤通信网存在的问题,以及多业务传输平台(MSTP)技术的实际应用,将155Mb/s光纤传输网升级至2.5Gb/s的原因、条件以及必要性和合理性。并就逐步升级的方案进行了优化。