一种基于准浮栅技术的0.6V,2.4GHz CMOS混频器

讨论分析了准浮栅晶体管的工作原理、电气特性及其等效电路.基于准浮栅NMOS晶体管,对Gilbert混频器电路结构进行改进设计,实现了超低压混频器.基于TSMC 0.25μm CMOS工艺的BSIM3V3模型,采用Hspice对混频器进行了仿真,仿真结果显示,该混频器在0.6V的单电源电压下,仍可以对2.4GHz的正弦信号进行混频,转换增益为-21.8dB,三阶输入截止点的值为34.6dB.     

一种基于衬底驱动技术的亚1V CMOS混频器

讨论了衬底驱动的工作原理。基于衬底驱动NMOS晶体管,对Gilbert混频器电路结构进行改进设计,实现了超低压混频器。基于TSMC 0.25μm CMOS工艺的BSIM3V3模型,采用Hspice,对混频器进行了仿真。结果显示,该混频器在0.8 V单电源电压下,仍可以对2.4 GHz的正弦信号进行混频,转换增益为-8.5 dB,三阶输入截止点的值为28.4 dB。     

一种基于衬底驱动技术的超低压模拟混频器

讨论分析了混频器和衬底驱动MOSFET的工作原理.在此技术基础上设计一个低压模拟混频器.基于TSMC 0.25 μm CMOS工艺BSIM3V3模型,采用Hspice对整个电路进行仿真.仿真结果表明,该混频器在1.2V的单电源电压下,可以实现对2.4GHz正弦信号的混频,转换增益为-12.8dB,三阶输入截止点的值为23dB.     

一种0.9V低电压低本振功率CMOS有源混频器

设计了一种可工作于0.9 V低电压和-5 dBm本振功率的CMOS有源混频器.通过在MOS管栅极和衬底间引入耦合电容,利用衬底效应加快MOS管的导通和截止,使开关对的开关状态更理想,有效地降低混频器的噪声并提高其线性特性.采用0.18 μm CMOS工艺设计,在2.45 GHz本振信号和2.44 GHz射频信号输入下,实验结果表明该混频器可有效地实现混频且具有较好的性能指标:电压转换增益为12.4 dB,输入三阶截断点为-0.6 dBm,输入1dB压缩点为-3.4 dBm,单边带噪声系数为12 dB.     

一种基于0.18-μm CMOS 工艺的超宽频带分布式无源栅注入混频器

本文介绍了一种基于0.18-μm CMOS 工艺的宽带无源分布式栅注入混频器。通过采用分布式拓扑结构,该混频器具有很宽的工作频带;中频输出端口使用了一个4阶低通滤波器,从而极大地提高端口之间的隔离度。此外,文中还分析了混频器的阻抗匹配与转换损耗。测试表明：该混频器在3GHz到40GHz频率范围工作时的转换损耗为 9.4 ~ 17 dB,零直流功耗,其芯片面积为0.78 mm2。在射频频率为23GHz固定中频频率为500MHz时的输入参考1dB压缩点大于4dBm。在整个工作频带内,其射频到本振端口、射频到中频端口及本振到中频端口的隔离度分别大于21dB, 38dB,45dB。该混频器适用于WLAN,UWB,Wi-Max,车载雷达系统和其它毫米波射频的相关应用。     

一种2.4GHz 0.35μm CMOS Gilbert下变频器

利用0.35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器．其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2.452GHz,2.45GHz和2MHz．测试表明：在3.3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为－11dBm．     

5.8 GHz CMOS混频器设计

介绍了CMOS混频器主要技术指标的设计思路和技术.采用O.18 μm CMOS工艺,使用Agilent公司的ADS软件设计出一种5.8 GHz CMOS混频器电路,结果表明,工作电压1.8 V时,RF频率5.8 GHz,本振频率5.78 GHz,中频频率20 MHz下,转换增益7.3 dB、输入1 dB压缩点-8.3 dBm,噪声系数8.7,工作电流小于5 mA,该电路已交付流片.     

一种2.4GHz 0.35μm CMOS Gilbert下变频器

利用0.35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器.其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2.452GHz,2.45GHz和2MHz.测试表明:在3.3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为-11dBm.     

2.4GHz 0.35μm CMOS Gilbert下变频器

利用0 35μm CMOS工艺实现了一种用于低中频接收机的Gilbert型下变频器.其中,混频器的输出级采用折叠级联输出,射频信号、本振信号和中频信号的频率分别为2 452GHz,2 45GHz和2MHz.测试表明:在3 3V电源电压条件下,整个混频器电路消耗的电流约为4mA,转换增益超过6dB,输入1dB压缩点约为-11dBm.     

一种300 GHz CMOS高增益谐波混频器

基于TSMC 65 nm CMOS工艺,设计了一种工作在300 GHz的高增益、3阶谐波混频器。在谐波混频器中,提出将射频电感与接收天线设计为一体的新思路,不仅避免了二者之间的匹配,还减小了芯片尺寸。该谐波混频器包括片上天线、混频模块、IF放大器等。仿真结果表明,片上环形天线的谐振频率点在300 GHz附近,射频电感在300 GHz附近为21.9 pH,混频模块的转换增益为－5.4 dB,IF放大器的电压增益为23.5 dB,谐波混频器的最大转换增益为14.9 dB。当谐波混频器的转换增益大于0 dB时,输出频率带宽为0.05~12.47 GHz。     

A 51 to 65 GHz Low-Power Bulk-Driven Mixer Using 0.13 $mu$m CMOS Technology

A low-voltage and low-power down-conversion bulk-driven mixer using standard 0.13 $mu$ m CMOS technology is presented in this letter. To work on a low supply voltage and low power consumption applications while maintaining reasonable performance, the bulk-driven technique is selected in this V-band mixer design. The mixer has a conversion gain of $0 pm 1.5$ dB from 51 to 65 GHz with low supply voltage of 1 V and low power consumption of 3 mW. To our knowledge, the MMIC is the highest frequency CMOS bulk-driven mixer to date with good conversion gain and low power consumption among the recently published active mixers around 60 GHz.      

A 10–35 GHz Low Power Bulk-DrivenMixer Using 0.13 $mu$m CMOS Process

10-35 GHz doubly balanced mixer using a 0.13-mum CMOS foundry process is presented in this letter. Using the bulk-driven topology, the number of transistors of the doubly balanced mixer is reduced; thus the mixer can achieve a low supply voltage and low power consumption. This bulk-driven mixer exhibits a measured conversion gain of -1 plusmn 2 dB from 10 to 35 GHz of radio frequency (RF) with a fixed intermediate frequency (IF) of 100 MHz. The measured local oscillation (LO) to IF and RF-IF isolations are better than 30 dB. The chip area of the mixer is 0.6 times 0.4 mm². The total power consumption included output buffer is only 6 mW.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

一种新型的基于GSM1900标准的1.9GHz CMOS混频器

介绍了一种0.18μm CMOS工艺基于GSM1900(PCS1900)标准低中频接收机中的混频器.该混频器采用了一种新型的折叠式吉尔伯特单元结构.在3.3V电源电压、中频频率为100kHz的情况下,该混频器达到了6dB的转换增益,18.5dB的噪声系数(1MHz中频)和11.5dBm IIP3的高线性度,同时仅消耗7mA电流.     

一种低噪声高线性度CMOS上变频混频器

设计实现了一种采用开关跨导型结构的低噪声高线性度上变频混频器,详细分析了电路的噪声特性和线性度等性能参数,本振频率为900 MHz。芯片采用0.18μm Mixed signal CMOS工艺实现。测试结果表明,混频器的转换增益约为8 dB,单边带噪声系数约为11 dB,输入参考三阶交调点(IIP3)约为10.5 dBm。芯片工作在1.8 V电源电压下,消耗的电流为10 mA,芯片总面积为0.63 mm×0.78 mm。     

A parallel structure for CMOS four-quadrant analog multipliers andits application to a 2-GHz RF downconversion mixer

A parallel structure for a CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed structure, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 μm N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under a single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV_p-p at both multiplier inputs. The -3 dB bandwidth is 2.2 MHz and the DC current is 2.3 mA. By using the proposed multiplier as a mixer-core and connecting a newly designed output buffer, a CMOS RF downconversion mixer is designed and implemented by 0.5 μm single-poly-double-metal N-well CMOS technology. The experimental results have shown that, under 3 V supply voltage and 2 dBm LO power, the mixer has -1 dB conversion gain, 2.2 GHz input bandwidth, 180 MHz output bandwidth, and 22 dB noise figure. Under the LO frequency 1.9 GHz and the total DC current 21 mA, the third-order input intercept point is +7.5 dBm and the input 1 dB compression point is -9 dBm     

Analysis and implementation of a CMOS even harmonic mixer with current reuse for heterodyne/direct conversion receivers

This paper presents a novel topology for the even harmonic mixer (EHM). The proposed mixer employs a current reuse circuit in the RF input stage to improve its linearity, and uses the double frequency technique in the LO input stage to overcome the leakage and dc offset problems for heterodyne and direct conversion receivers, respectively. In addition, the proposed topology also has the advantages of low power consumption and high conversion gain. In order to demonstrate the benefits of the proposed mixer, theoretical analyses of linearity, conversion gain, and noise performance have been described in detail. The measured results reveal that the proposed mixer has a single-end conversion gain of 9.17 dB, third-order input intercept point (IIP/sub 3/) of -5.01 dBm, and IIP/sub 3//dc of -6.31 dB, under the supply voltage of 1.8 V, power consumption of 1.35 mW, and LO power of 5 dBm at 900 MHz.     

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 $mu$m CMOS

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 $mu$m CMOS process and occupies an active chip area of 1.1 mm $^{2}$. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of ${-}$12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.      

一种电流注入式零中频正交混频器

设计了一种用于900MHz RFID阅读器的零中频正交下变频混频器,该混频器采用共跨导级正交结构,并利用电流注入技术减小噪声,在UMC0.18μmCMOS工艺下实现。整个芯片分为三部分,混频器、带隙基准以及缓冲器,总面积为1.1mm2。混频器在1.8V电压下消耗电流3.7mA,带宽范围880～940MHz,增益16.42dB,三阶截点为-4.625dBm,在100kHz处噪声系数为15.2dB。芯片能够达到阅读器的性能要求。     

A CMOS Ku-Band 4x Subharmonic Mixer

In this work, the design and measurement of a new 4x subharmonic mixer circuit is presented using CMOS 0.18 m technology. With an RF input signal at 12.1 GHz, and an LO signal at 3.0 GHz, an intermediate frequency of 100 MHz is produced (f_IF = f_RF - 4f_LO). The mixer uses a modified Gilbert-cell topology with octet-phase LO switching transistors to perform the quadruple subharmonic mixing. Included in the design is an active balun for the RF signal and a circuit that generates an octet-phase LO signals from a differential input. The mixer has a conversion gain of approximately 6 dB, 1-dB compression point of -12 dBm, IIP3 of -2 dBm, and IIP2 of 17 dBm. The circuit also exhibits excellent isolation between its ports (e.g. LO-RF: 71 dB, 4LO-RF: 59 dB).