有机封装基板的芯片埋置技术研究进展

有机封装基板为IC提供支持、保护和电互联,是IC封装最关键的材料之一。系统级、微型化和低成本是IC封装的趋势,将有源、无源元件埋入封装基板,可以充分利用基板内部空间,释放更多表面空间,是减小系统封装体积的重要途径,因此有机封装基板的芯片埋置技术发展迅速。主要介绍有机封装基板的埋置技术发展过程,归纳了有机基板芯片埋置工艺路线类型,着重介绍了近十年不同的芯片埋置技术方案及其应用领域。在此基础上,对有机封装基板的埋置技术研究前景进行了展望。     

高密度多芯片集成电路封装技术

本文介绍了多芯片封装技术和工艺方案，包含系统功能设计、物理设计、版图验证，电学热学分析和基板工艺技术，及其市场发展趋势。     

高密度封装进展之三——SiP与SoC

哪种方式更能提高LST的附加值?是SiP(system in a package)还是SoC(system on a chip)?LSI厂家正对此进行激烈争论。作为系统集成的选择方式,LSI厂家一直集中力量致力于SoC的开发。但是LSI厂家发现,仅靠SoC这一条路线已不能满足用户的要求。目前,对于各大LSI厂家来说,要不要转换其发展资源的投入方向,需要当机立断。     

多芯片组件的封装技术

本文介绍了多芯片组件封装的结构类型，以及不同于混合微电路组件封装的典型要求；指出了多芯片封装常用材料，并以封装实例加以说明。     

系统级封装技术综述

介绍了系统级封装SiP如何将多块集成电路芯片和其他的分立元件集成在同一个封装内,有效解决了传统封装面临的带宽、互连延迟、功耗和集成度方面的难题.同时将SiP与系统级芯片SoC相比较,指出各自的特点和发展趋势.     

高密度封装进展之二——半导体封装技术的发展趋势

本文从超小型封装、超多端子封装、多芯片封装等几个方向介绍了半导体封装技术的发展趋势     

高密度封装进展之一元件全部埋入基板内部的系统集成封装（上）

将无源元件及IC等全部埋入基板内部的三维封装,不仅能提高电子设备的整体性能,有利于轻薄短小化,而且 由于钎焊连接部位减少,可提高可靠性并能有效降低封装的总价格。     

高密度封装

本文介绍了微电路的几种高密度封装,着重介绍当今最盛行的多芯片封装(MCP)、最新的片内系统(SIP)及三维封装等,并指出这是一种实现片上系统的变通方法。     

Microwave Plasmatrons for Fabrication of High-Density Integrated Circuits

Interaction between a high-power microwave and a planar layer of a low-pressure magnetoactive plasma under electron cyclotron resonance (ECR) conditions was studied. Results of numerical simulation of the one-dimensional problem are presented. Two modes of wave–plasma interaction were found. The use of these modes and their associated microwave plasmatrons in fabricating high-density ICs is discussed.     

高线密度X射线透射光栅的制作工艺

采用电子束光刻、X射线光刻和微电镀技术,成功制作了面积为10mm×0.5 mm,周期为500nm,占空比为1∶1,金吸收体厚度为430nm的可用于X射线衍射的大面积透射光栅.首先利用电子束光刻和微电镀技术制备基于镂空薄膜结构的X射线光刻掩模,然后利用X射线光刻经济、高效地复制X射线透射光栅.整个工艺流程分别利用了电子束光刻分辨率高和X射线光刻效率高的优点,并且可以得到剖面陡直的纳米级光栅线条.最后,测量了制作出的X射线透射光栅对波长为11nm同步辐射光的衍射峰,实验结果表明该光栅具有良好的衍射特性.     

高线密度X射线透射光栅的制作工艺

采用电子束光刻、X射线光刻和微电镀技术,成功制作了面积为10mm×0.5 mm,周期为500nm,占空比为1∶1,金吸收体厚度为430nm的可用于X射线衍射的大面积透射光栅.首先利用电子束光刻和微电镀技术制备基于镂空薄膜结构的X射线光刻掩模,然后利用X射线光刻经济、高效地复制X射线透射光栅.整个工艺流程分别利用了电子束光刻分辨率高和X射线光刻效率高的优点,并且可以得到剖面陡直的纳米级光栅线条.最后,测量了制作出的X射线透射光栅对波长为11nm同步辐射光的衍射峰,实验结果表明该光栅具有良好的衍射特性.     

射频系统的系统级封装

论述了高速数据处理和高密度封装技术的特点及对射频系统封装的特殊要求,介绍了射频系统封装的基本技术和一种包含LNA、PPA、滤波器及天线开关的射频系统级封装模块.概述了射频系统级封装的设计、仿真和测试的方法和步骤.     

基于系统级封装(SiP)的信息安全芯片集成设计

为了解决信息安全系统中,逻辑运算芯片与存储器难以实现集成的问题,并更充分地满足信息安全系统高性能、低功耗、高可靠性的要求,本文提出了"基于SiP的信息安全芯片集成"的概念及具体设计方案.根据此方案设计实现了一款集成CPU、Flash存储器、密码算法芯片的小型信息安全系统的SiP成品实例,该成品的功能和性能验证结果均满足系统的目标需求,从而证实了该设计方案的可行性.该方案也符合今后电子技术和信息安全系统的主要发展方向.     

Inkjet printed System-in-Package design and manufacturing

Additive manufacturing technology using inkjet offers several improvements to electronics manufacturing compared to current non-additive masking technologies. Manufacturing processes can be made more efficient, straightforward and flexible compared to subtractive masking processes, several time-consuming and expensive steps can be omitted. Due to the additive process, material loss is minimal, because material is never removed as with etching processes. The amounts of used material and waste are smaller, which is advantageous in both productivity and environmental means. Furthermore, the additive inkjet manufacturing process is flexible allowing fast prototyping, easy design changes and personalization of products. Additive inkjet processing offers new possibilities to electronics integration, by enabling direct writing on various surfaces, and component interconnection without a specific substrate. The design and manufacturing of inkjet printed modules differs notably from the traditional way to manufacture electronics. In this study a multilayer inkjet interconnection process to integrate functional systems was demonstrated, and the issues regarding the design and manufacturing were considered.     

SIP封装技术现状与发展前景

SIP（System in Package）,指系统级封装。特点是将不同功能的有源电子元器件加上无源或类似MEMS的光学器件集中于一个单一封装体内,构成一个类似系统的器件为系统或子系统提供多种功能。它与系统级芯片（SOC）互补,实现混合集成,具有设计灵活、周期短、成本低的特点。文章通过系统封装技术的研发历程,评价了封装的优越性、探讨了此种封装技术的产品架构和相关技术及其发展前景。     

Signal Integrity Flow for System-in-Package and Package-on-Package Devices

As data rates required for systems in package (SiPs) increase and their complexity increases, signal integrity issues become increasingly difficult to address. The design flow of the SiP should therefore take into account these issues from the beginning. A design flow aimed at designing the SiP tracks is presented; its suitability for the design of packages comprising multiple stacked memories is verified through a design example. The proposed flow for signal integrity can be integrated easily within the complete design of the SiP.      

Watermark-Induced High-Density Via Failures in Submicron CMOS Fabrication (May 2006)

High via resistance was detected in the high-density via structure in our 0.15-mum back-end-of-line (BEOL) yield monitoring test vehicle. A localized insulating layer was found on top of the plug in test vehicle causing high via resistance. The failure was attributed to watermark-induced contaminants on top of the W plug. It was shown that the failure could be avoided by eliminating watermark formation on the wafer in the post-chemical-mechanical polishing scrub process.     

Three-Dimensional System-in-Package Using Stacked Silicon Platform Technology

In this paper, a novel method of fabricating three–dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.