北京正负电子对撞机次级束质子单粒子翻转计算和试验研究

北京正负电子对撞机(BEPC)电子直线加速器试验束打靶产生的次级束中包含质子,其中能量约为50MeV~100MeV的质子占有很大比例,这弥补了国内高能质子源的空白。本工作计算得到次级束中的质子能谱,建立质子单粒子翻转截面计算方法,在北京正负电子对撞机次级束质子辐射环境中,计算静态随机存取存储器的质子单粒子翻转截面,设计了SRAM质子单粒子翻转截面测试试验,发现SRAM单粒子翻转和注量有良好的线性,这是SRAM发生单粒子翻转的证据。统计得到不同特征尺寸下SRAM单粒子翻转截面,试验数据与计算结果相符,计算和试验结果表明随着器件特征尺寸的减小器件位单粒子翻转截面减小,但器件容量的增大,翻转截面依然增大,BEPC次级束中的质子束可以开展中高能质子单粒子效应测试。     

温度对SRAM器件单粒子翻转重离子测试的影响

本文基于单粒子效应地面重离子模拟实验,选取体硅SRAM与SOI SRAM两种待测器件,在兰州重离子加速器上（HIRLF）研究了温度对单粒子翻转测试的影响。用12C粒子对体硅SRAM器件的温度实验显示,单粒子翻转截面易受温度的影响。对于SOI SRAM器件,12C粒子测得的单粒子翻转截面随温度升高有显著的增大,但209Bi 粒子测得的单粒子翻转截面却随温度保持恒定。用Monte Carlo的方法分析了温度对单粒子翻转测试的影响规律,发现在单粒子翻转阈值LET附近温度对单粒子翻转截面有大的影响,但是随着单粒子翻转的发生接近于饱和,单粒子翻转截面渐渐的表现出低的温度依赖性。基于该模拟结果,我们对实验数据进行了分析,同时提出了一种准确评估在轨翻转率的合理方法。     

激光定位深亚微米CMOS SRAM单粒子翻转敏感区

The pulsed laser facility for SEU sensitivity mapping is utilized to study the SEU sensitive regions of a 0.18/zm CMOS SRAM cell. Combined with the device layout micrograph, SEU sensitivity maps of the SRAM cell are obtained. TCAD simulation work is performed to examine the SEU sensitivity characteristics of the SRAM cell. The laser mapping experiment results are discussed and compared with the electron micrograph information of the SRAM cell and the TCAD simulation results. The results present that the test technique is reliable and of high mapping precision for the deep submicron technology device.     

卫星光通信系统中单粒子翻转计算方法研究

高能带电粒子造成的单粒子翻转是影响卫星光通信系统性能的重要因素,给出了单粒子翻转的物理机制及主要研究方法。利用OMERE 3.4软件对星载CMOS 2164器件进行了单粒子翻转率计算,结果表明,通过对轨道倾角和轨道高度的优化设计可以有效减小卫星光通信系统中电子器件的单粒子翻转率。为了有效克服单粒子辐射效应,除了简单的增加屏蔽层厚度等防护方法外,还应考虑通过电子器件的选择来提高抗辐射性能。     

一种65 nm CMOS低功耗加固SRAM单元

提出了12管低功耗SRAM加固单元。基于堆叠结构,大幅度降低电路的泄漏电流,有效降低了电路功耗。基于两个稳定结构,可以有效容忍单粒子翻转引起的软错误。Hspice仿真结果表明,与相关加固结构相比,该结构的功耗平均下降31.09%,HSNM平均上升19.91%,RSNM平均上升97.34%,WSNM平均上升15.37%,全工作状态下均具有较高的静态噪声容限,表现出优秀的稳定性能。虽然面积开销平均增加了9.56%,但是,读时间平均下降14.27%,写时间平均下降18.40%,能够满足高速电子设备的需求。     

基于TSV转接板的3D SRAM单粒子多位翻转效应

为了研究硅通孔(TSV)转接板及重离子种类和能量对3D静态随机存储器(SRAM)单粒子多位翻转(MBU)效应的影响,建立了基于TSV转接板的2层堆叠3D封装SRAM模型,并选取6组相同线性能量传递(LET)值、不同能量的离子(¹¹B与^4He、²⁸Si与¹⁹F、⁵⁸Ni与²⁷Si、⁸⁶Kr与⁴⁰Ca、¹⁰⁷Ag与⁷⁴Ge、¹⁸¹Ta与¹³²Xe)进行蒙特卡洛仿真。结果表明,对于2层堆叠的TSV 3D封装SRAM,低能离子入射时,在Si路径下,下堆叠层SRAM多位翻转率比上堆叠层高,在TSV(Cu)路径下,下堆叠层SRAM多位翻转率比Si路径下更大;具有相同LET值的高能离子产生的影响较小。相比2D SRAM,在空间辐射环境中使用基于TSV转接板技术的3D封装SRAM时,需要进行更严格的评估。     

Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

Single event multiple-cell upsets (MCU) increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.     

Modeling and simulation of single-event effect in CMOS circuit

This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device (direct ionization and indirect ionization) are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices (bipolar transistor effect, charge sharing effect) and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients (SETs) in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed.     

Experimental research of heavy ion and proton induced single event effects for a Bi-CMOS technology DC/DC converter

This paper tested and analyzed heavy ion and proton induced single event effects (SEE) of a commercial DC/DC converter based on a 600 nm Bi-CMOS technology. Heavy ion induced single event transients (SET) testing has been carried out by using the Beijing HI-13 tandem accelerator at China Institute of Atomic Energy. Proton test has been carried out by using the Canadian TRIUMF proton accelerator. Both SET cross section versus linear energy transfer (LET) and proton energy has been measured. The main study conclusions are: (1) the DC/DC is both sensitive to heavy ion and proton radiations although at a pretty large feature size (600 nm), and threshold LET is about 0.06 MeV·mg/cm²; (2) heavy ion SET saturation cross section is about 5 magnitudes order larger than proton SET saturation cross section, which is consistent with the theory calculation result deduced by the RPP model and the proton nuclear reaction model; (3) on-orbit soft error rate (SER) prediction showed, on GEO orbit, proton induced SERs calculated by the heavy ion derived model are 4-5 times larger than those calculated by proton test data.     

Experimental study on the single event effects in pulse width modulators by laser testing

This paper presents single event effect (SEE) characteristics of UC1845AJ pulse width modulators (PWMs) by laser testing. In combination with analysis to map PWM circuitry in the microchip dies, the typical SEE response waveforms for laser pulses located in different circuit blocks of UC1845AJ are obtained and the SEE mechanisms are analyzed. The laser SEE test results show that there are some differences in the SEE mechanisms of different circuit blocks, and phase shifts or changes in the duty cycles of few output pulses are the main SEE behaviors for UC1845AJ. In addition, a new SEE behavior which manifests as changes in the duty cycles of many output pulses is revealed. This means that an SEE hardened design should be considered.     

SRAM型FPGA中SEM IP核的验证与自动注错方法

星载设备长时间工作在空间环境中,宇宙中的带电粒子会造成器件功能异常,产生存储器软错误,严重时会损坏硬件电路.为模拟辐照环境对器件的影响,利用Xilinx公司的软错误缓解(SEM)控制器IP核,搭建了基于Xilinx Kintex-7的验证与测试平台,完成对SEM IP核的功能验证.为提高测试效率,设计了基于上述平台的自动注错方法.经过验证,该方法能够达到预期的帧地址覆盖率.实验结果表明,SEM IP核具备软错误注入与缓解功能,自动注错方法有利于此IP核的实际应用.     

基于Geant4的三维半导体器件单粒子效应仿真

在空间中,辐射粒子入射半导体器件,会在器件中淀积电荷.这些电荷被器件的敏感区域收集,造成存储器件(如静态随机存储器(SRAM))逻辑状态发生变化,产生单粒子翻转(SEU)效应.蒙特卡洛工具-Geant4能够针对上述物理过程进行计算机数值模拟,可以用于抗辐射器件的性能评估与优化.几何描述标示语言(GDML)能够在Geant4环境下对器件模型进行描述.通过使用GDML建立三维的器件结构模型,并使用Geant4进行不同能量质子入射三维器件模型的仿真.实验结果表明,在三维器件仿真中低能质子要比高能质子更容易引起器件的单粒子翻转效应.