基于电阻电流镜的低压灵敏放大器设计

提出一种适用于低压快闪存储器的电流模式的低压灵敏放大器.该灵敏放大器在基准电流产生电路中使用电阻电流镜代替传统的晶体管电流镜,使得基准电流产生电路的工作电压减少了一个阈值电压,从而降低灵敏放大器的工作电压.位线电压控制电路中运算放大器的使用减少了由于温度和工艺变化所引起的位线电压变化,进而提高读取操作的精度.采用中芯国际90nm工艺设计,提出的灵敏放大器在1.2V电源电压时的读取时间是14.7ns,相对于传统的结构,单个灵敏放大器的功耗被优化了13%.     

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 ℃.     

Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

A novel bitline sensing scheme is proposed for low-voltage DRAM to achieve low power dissipation and compatibility with low-voltage CMOS. One of the major obstacles in low-voltage DRAM is the degradation of data-retention time due to low signal level at the memory cell, which requires power-consuming refresh operations more frequently. This paper proposes an offset-cancellation sense-amplifier scheme (OCSA) that improves data-retention time significantly even at low supply voltage. It also improves die efficiency, because the proposed scheme reduces the number of sense amplifiers by supporting more cells in each sense amplifier. Measurements show that the data-retention time of the proposed scheme at 1.5-V supply voltage is 2.4 times of the conventional scheme at 2.0 V.     

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique

A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5-μm CMOS/SIMOX technology. A newly introduced “FD-PD mode switching” transistor dynamically switches its operation mode between fully depleted (FD) and partially depleted (PD) according to the body bias voltage, thus it has both PD-mode large current drivability and FD-mode small leakage current. By the body bias control, the transistor operates as if it has an S-factor of 30 mV/decade. Enabling both high speed and low power at a low voltage, 30 mV is only one-half the theoretical value. By utilizing the transistor, we have developed body pulsed sense amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current     

A 2-V 10.7-MHz CMOS limiting amplifier/RSSI

This paper presents low-voltage low-power CMOS circuit design techniques for an intermediate frequency (IF) limiting amplifier and received signal strength indicator (RSSI). The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified speed, overall gain, and accuracy. Each gain cell of the limiting amplifier employs folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the signal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and low power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. The prototype occupies an active area of 0.4 mm² using a 0.6-μm digital CMOS technology. The power dissipation is 6.2 mW     

一种低压分段线性曲率校正CMOS带隙基准源设计

在传统低压带隙基准的基础上,通过设计与热力学温度成正比的电流(IPTAT)及与热力学温度呈互补关系的电流(ICTAT),实现节点电流相减,从而产生分段线性电流作为基准源的曲率校正分量,设计了一个性能更佳的曲率校正带隙基准。电路采用低压运放及低压PTAT电流产生模块,工作电压低。Cadence仿真结果显示,在-40~125℃温度范围内,平均温度系数大约3×10-6℃-1,最低工作电压在1 V左右,可用于低电源电压、高精度的集成芯片。     

高速低功耗电流型灵敏放大器的设计

提出了一款适合在低电压、大容量SRAM中应用的高速低功耗电流型灵敏放大器。该电路在交叉耦合反相器之间添加了一对隔离管,有效消除了大量位线寄生电容所带来的负面影响,从而极大提高了灵敏放大器的速度。同时,通过对时序控制电路的优化,有效降低了放大器的功耗。采用SMIC0．13μm数字工艺在HSpice下进行仿真,结果表明：在室温,1．2V工作电压下,灵敏放大器的放大延迟仅为0．344ns,功耗为102μw。相比文献中提出的电流型灵敏放大器,速度分别提高了9．47％和31．2％,功耗则降低了64．8％与63％。     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

1.2-V CMOS op-amp with a dynamically biased output stage

A very low-voltage operational amplifier in a standard CMOS process with a 0.75 V threshold voltage is presented. It uses a novel dynamically biased output stage based on the switched-capacitor approach. Thanks to this, drive performance is greatly improved and accurate current control is also achieved. The amplifier is capable of working with a power supply as low as 1.2 V while providing a -74 dB total harmonic distortion with a 700 mV peak-to-peak output voltage into a 500 Ω and 20 pF output load. The open-loop gain and the gain-bandwidth product are higher than 90 dB and 2.2 MHz, respectively     

A 900-mV low-power ΔΣ A/D converter with 77-dB dynamicrange

The design of a low-voltage and low-power ΔΣ analog-to-digital (A/D) converter is presented. A third-order single-loop ΔΣ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV ΔΣ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-μW power consumption     

基于LDO电压调整器的带隙基准电压源设计

设计一款应用于电压调整器（LDO）的带隙基准电压源。电压基准是模拟电路设计必不可缺少的一个单元模块,带隙基准电压源为LDO提供一个精确的参考电压,是LDO系统设计关键模块之一。本文设计的带隙基准电压源采用0.5μm标准的CMOS工艺实现。为了提高电压抑制性,采用了低压共源共栅的电流镜结构,并且在基准内部设计了一个运算放大器,合理的运放设计进一步提高了电源抑制性。基于Cadence的Spectre进行前仿真验证,结果表明该带隙基准电压源具有较低的变化率、较小的温漂系数和较高的电源抑制比,其对抗电源变化和温度变化特性较好。     

Design of a 1-V High-Frequency Bipolar Operational Amplifier

This paper presents the design of a low-voltage high-frequency operational amplifier implemented in bipolar technology. The minimum power supply voltage for this amplifier can be as low as 0.9 V, so it is suitable for portable equipment applications. The design emphasis is on the high frequency response. A pole-zero cancellation compensation technique and a special low-voltage design gives a simulated cutoff frequency of about 175 MHz with a 50° phase margin at a power supply voltage of ±0.5 V with a 10 k load resistance; the low-frequency voltage gain is 110 dB. The common-mode input range includes, and can exceed, the negative supply voltage by about 400 mV. A complimentary class-B type output stage enables the output voltage to reach both supply rails within about 100 mV without significant signal distortion. This amplifier dissipates 875 W.     

A high-performance very low-voltage current sense amplifier for nonvolatile memories

A high-performance sense amplifier for nonvolatile memories capable of working under a very low-voltage power supply is presented. The topology of the sense amplifier uses a pure current-mode comparison allowing power supplies lower than 1 V to be used and includes two subcircuits which improve slew rate performance. The sense amplifier was implemented in an EEPROM realized with a 0.18-/spl mu/m EEPROM technology. Experimental results showed a read access time of about 30 ns with a power supply of 1.65 V.     

Transconductance improvement method for low-voltage bulk-driven input stage

A proposed transconductance enhanced method for low-voltage bulk-driven input stage is presented in this paper. The basic idea is to use current–shunt auxiliary amplifier to improve the voltage gain from the inputs to the gates of bulk-driven pairs. The enhanced voltage gain of the auxiliary amplifier leads to the improvement of the effective transconductance of the input stage. Results show that the transconductance of the OTA using the proposed bulk-driven input stage improves almost 200% without additional power and area dissipation compared to the conventional bulk-driven counterpart.     

一种高可靠电流灵敏放大器设计

提出了一种带反馈放大器的电流灵敏放大器 ,将用于放大的 NMOS管同时作为位线多路选择器( MU X) ,与一般的电流灵敏放大器相比 ,延迟时间更短 ,而且更适于低电源电压工作。同时分析了阈值电压失配对电流灵敏放大器的影响 ,结果表明 ,失配不仅可能增大灵敏放大器时延 ,甚至造成误放大 ;带反馈放大器的电流灵敏放大器能够有效地抑制阈值失配的影响 ,其性能和可靠性良好。     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

A high performance sense amplifier for a 5 V dynamic RAM

Increasing dynamic RAM cell density and the use of a single low-voltage power supply have made it mandatory to store the full power supply voltage in the cell and to be able to detect smaller signals reliably with the initial sense amplifier. The authors present a circuit design approach that restores the cell to a full V/SUB DD/ `1' level, preamplifies the initial charge imbalance before sensing by conventional techniques, and is used in the Fairchild 64K design. Design requirements and a detailed analysis of the amplifier are presented along with simulated results, followed by performance data. The circuit analysis shows how the key design parameters should be chosen and the effects of clock timing variations on the performance of the sense amplifier.     

Gated-diode amplifiers

This brief describes MOS amplifiers comprising a gated diode and a field-effect transistor. A gated diode is a two-terminal MOS device in which charge is stored when a voltage above the threshold voltage is applied between the gate and the source, and negligible charge is stored otherwise. The operation makes use of the nonlinear capacitance of the gated diode for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain, signal margin, and current drive. Further, a number of small-signal single-ended sense amplifier circuits are presented. The gated-diode sense amplifiers deliver high gain, require low power and low device count, and are tolerant to voltage and process variation.     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

A 0.8 V CMOS amplifier design

A low-voltage operational amplifier design in a standard CMOS process is presented for operation at ±0.4 V. The design incorporates a low voltage level shift current mirror using forward body-biased MOSFETs limited to a maximum of 0.4 V to minimize latchup and hot carrier effects. Some of the measured performances are as follows: 58 dB open-loop gain, 30 kHz bandwidth, 50° phase margin and 80 μW power dissipation and are in close agreement with the corresponding design and SPICE simulated values.