可嵌入式应用的新型2T结构硅纳米晶存储器

本文研究了2T硅纳米晶非挥发存储器性能和可靠性。存储单元可获得良好性能,包括低压操作下快速的擦写速度,卓越的数据保持特性（保持10年）,良好的耐受性（10k次擦写周期以后小于10%的阈值电压飘移）。数据表明了此器件在未来嵌入式非挥发存储应用的可能性。     

Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

n metal oxide semiconductor (MOS)capacitors fabricated by the former method, which are much better than 4.6 Ⅴ and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

面向非挥发存储器应用的叠层Ru纳米晶材料的制备与特性

Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor （MOS） capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

低温工艺硅量子点多晶硅TFT非易失性存储器

This paper reports on a successful demonstration of poly-Si TFT nonvolatile memory with a much reduced thermal-budget.The TFT uses uniform Si quantum-dots(size ¹0 nm and density ¹0¹¹ cm^-2) as storage media,obtained via LPCVD by flashing SiH₄/H₂ at 580℃for 15 s on a Si₃N₄ surface.The poly-Si grain-enlargement step was shifted after source/drain formation.The NiSi_x-silicided source/drain enables a fast lateral-recrystallization,and thus grain-enlargement can be accomplished by a much reduced thermal-cycle（i.e., 550℃/4 h）.The excellent memory characteristics suggest that the proposed poly-Si TFT Si quantum-dot memory and associated processes are promising for use in wider TFT applications,such as system-on-glass.     

A novel sourceline voltage compensation circuit for embedded NOR flash memory

A novel sourceline voltage compensation circuit for program operation in embedded flash memory is presented. With the sourceline voltage compensation circuit, the charge pump can modulate the output voltage according to the number of cells to be programmed with data ＂0＂. So the IR drop on the sourceline decoding path is compensated, and a stable sourceline voltage can be obtained. In order to reduce the power dissipation in program operation, a bit-inversion program circuit is adopted. By using the bit-inversion program circuit, the cells programmed to data ＂0＂ are limited to half of the bits of a write data word, thus power dissipation in program operation is greatly reduced. A 1.8-V 8 × 64-kbits embedded NOR flash memory employing the two circuits has been integrated using a GSMC 0.18-μm 4-poly 4-metal CMOS process.     

使用化学方法常温合成金纳米晶并通过旋涂工艺将其组装的存储特性可调型非易失性存储器

3C行业的不断发展,催生了对高密度、持久保存、快速擦写、鲁棒可靠性的非易失性存储器(如flash)的持续需求,促使我们在科研上不断地深入研究新材料、新工艺。在本文中,我们首次采用了区别于传统CMOS工艺的两步工艺方法来制作金属纳米晶非易失性存储器。这种方法,由于将金纳米晶的化学合成和后续组装分离开来,所以能够独立地调节纳米晶的尺寸和组装密度,而且可以很好地避免一直困扰的金属扩散问题。最终的形貌表征和电学测量结果,证实存在一个最优化的纳米晶密度--在这个最优化条件下,我们的存储器件,既有持久的保存时间,又有较大的存储窗口。而组装密度的可调,同时可以满足我们对于大的存储窗口/较长保存时间某一方面的偏好。这些实验结果,都很好地证明了我们两步工艺方法的可行性。     

Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

A novel two-step method is employed,for the first time,to fabricate nonvolatile memory devices that have metal nanocrystals.First,size-averaged Au nanocrystals are synthesized chemically;second,they are assembled into memory devices by a spin-coating technique at room temperature.This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually.In addition,processes at room temperature prevent Au diffusion,which is a main concern for the application of...     

一种适用于低压高速嵌入式应用的2T P沟道纳米晶存储器件

本文基于嵌入式应用的低压、高速要求,提出了一种基于2T结构的P沟道纳米晶存储新型结构。该器件采用带带隧穿激发热电子注入(BTBTIHE)的编程方式,可以同时实现高速、低功耗编程。同时采用2T结构以简化外围高压和读出电路。该器件具有良好的存储特性,包括高编程速度（5us编程脉冲下获得1.1V窗口）和优异的数据保持特性（在10年的保持时间电荷损失仅为20%）。该器件在嵌入式非挥发存储领域具有很强的应用潜力。     

新型的形状记忆合金／硅薄膜微驱动器

介绍了一种用硅微加工技术制作的ＮｉＴｉ／Ｓｉ 薄膜结构的双向微驱动器。它利用ＮｉＴｉ 形状记忆合金薄膜（ＳＭＡ） 大的相变回复应力和Ｓｉ 衬底膜的反偏置力产生有一定位移量的双向运动。对ＮｉＴｉ 薄膜进行合理的图形化后使得驱动器位移量增大,双向效应显著,响应速度提高。同时图形化后的ＮｉＴｉ 膜也是加热电阻,使驱动结构简单,所需功率减少。驱动器实际驱动面积为３ ×３ｍ ｍ２ 厚度为２０μｍ 。可产生的最大位移为５０μｍ ,最高驱动频率可达１００Ｈｚ。驱动功率可减小到２００ｍ Ｗ。经过１０００ 万次振动后,驱动膜无开裂,性能正常。它已被成功的应用于压缩型微泵,该泵最大流量达３４０μＬ／ｍｉｎ 。     

基于虚拟存储的嵌入式存储系统的设计方法

借鉴计算机系统设计中的虚拟存储体系,采用页面分组和虚拟接口技术,以8051系列单片机为例实现了一个具有256k程序区、128k数据区的存储系统。本方法不仅极大地扩展了系统存储空间,还增强了操作系统的透明性。     

Enhanced operation and retention characteristics in charge-trapping flash memory device with a novel Si/Ge super-lattice channel

Charge-trapping flash memory devices with super-lattice channels having different stacking structures and thicknesses of Ge top-layer are investigated in this work. Both programming and erasing speeds are significantly improved for devices with super-lattice channels. Programming speed increases with increasing thickness of Ge layer in the super-lattice channel. The enhancement on programming speed can be achieved up to 40 times or better. For devices with Ge top-layer on super-lattice channel, a further enhancement is observed with increasing Ge thickness. The retention characteristic of devices with super-lattice channel is better than that with Si-channel devices owing to the slightly increased thickness of tunneling oxide.     

Characterisation of a new hump-free device structure for smart power and embedded memory technologies

A new device structure suitable for smart power and embedded memory technologies is presented that provides ideal hump-free subthreshold behaviour for shallow trench isolations by locally thickening the gate dielectric. This device structure is compared with an alternative approach to remove the hump effect, an improved process that reduces the oxide recess of the isolating trench. The new device offers a superior subthreshold slope. Emphasis has been placed not only on the hump effect but also on the reliability characterisation. The gate integrity of the new structure is comparable and only a minor degradation of the hot-carrier lifetime is observed. The new device structure provides an easy way to remove the hump without any change in the process and is applicable to every technology that offers more than one gate dielectric.     

A donor-acceptor structured conjugated copolymer for flexible memory device

A Donor-Acceptor structured conjugated copolymer PCNCzF was designed and synthesized for flexible polymer memory. The fabricated Al/PCNCzF/ITO-coated PET device exhibited non-volatile WORM memory effect, with the switch-on threshold voltage of −1.4 V, and an ON/OFF current ratio of more than 10⁴. The reliability and mechanical stability of the flexible memory device was deduced from the endurance and bending tests. Theoretical simulation, in-situ fluorescence spectra, as well as C-AFM measurements were employed to evaluate the switching mechanism of the memory device. The present flexible memory device was expected to meet the demand for flexible electronics applications.     

Growth ambient on memory characteristics in Au nanoclusters embedded in high-k dielectric as novel non-volatile memory

In this work, we report on the findings of the effects of different ambient on memory characteristics of a floating gate memory structure containing HfAlO control gate, self-organized Au nanoclusters (NCs), and a HfAlO tunnel layer deposited by the pulsed-laser deposition. The optimized fabrication environment has been found and stored charge density up to 10¹³ cm⁻² has been achieved. As the sizes of the Au NCs are smaller than 4 nm, they may be potentially used in multilayer-structured multi-bit memory cell.     

一种适应于高性能嵌入式闪存的低压灵敏放大器

本文提出了一种适应于高性能嵌入式闪存的低压灵敏放大器,通过采用电流比较技术和自动消失调技术,该灵敏放大器在低电源电压下获得了很好的性能,改善了低电流阈值窗口存储器的读取速度。基于上海宏力半导体制造公司130nm的嵌入式闪存工艺,该灵敏放大器的感应时间在1.5V的电源电压下达到了0.43ns,其感应速度比传统的灵敏放大器提高了46%     

A low-voltage sense amplifier for high-performance embedded flash memory

This paper presents a sense amplifier scheme for low-voltage embedded flash(eFlash)memory applications.The topology of the sense amplifier is based on current mode comparison.Moreover,an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current.The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process,and the sense time is 0.43 ns at 1.5 V,corresponding to a46% improvement over the conventional technologies.     

Solution-processed flexible nonvolatile organic field-effect transistor memory using polymer electret

Flexible organic field-effect-transistor (OFET) memory is one of the promising candidates for next-generation wearable nonvolatile data storage due to its low price, solution-processability, light-weight, mechanically flexibility, and tunable energy level via molecular tailoring. In this paper, we report flexible nonvolatile OFET memory devices fabricated with solution-processed polystyrene-brush electret and organic semiconductor blends of p-channel 6, 13-bis-(triisopropylsilylethynyl)pentacene (TIPS-PEN) and n-channel poly-{[N,N′-bis(2- octyldodecyl)-naphthalene-1,4,5,8-bis-(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)} (P-(NDI2OD-2T); N2200). Fabricated flexible OFET memory devices exhibited high memory window (30 V) and ON/OFF current ratio (memory ratio) over 10³. Furthermore, we obtained reliable memory ratio (~10³) over retention time of 10⁸ s, 100 times of repeated programming/erasing cycles, and 1000 times of bending tests at a radius of 3 mm.     

Low-voltage programmable/erasable high performance flexible organic transistor nonvolatile memory based on a tetratetracontane passivated ferroelectric terpolymer

Future flexible electronic systems require memory devices combining low power consumption and mechanical bendability. However, high programming/erasing (P/E) voltages, which are universally required to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a novel route to achieve a low-voltage programmable/erasable flexible Fe-OFET NVM. Ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)], rather than the conventional ferroelectric copolymer poly(vinylidene-fluoride-trifluoroethylene) [P(VDF-TrFE)], is used as the gate dielectric. The low coercive field of P(VDF-TrFE-CTFE) is the main contribution to the low-voltage operation in the Fe-OFET NVM, even with a relative thick ferroelectric gate dielectric layer. By depositing a long-chain alkane molecule Tetratetracontane (TTC) as the passivation layer on the surface of P(VDF-TrFE-CTFE) film, the layer-by-layer growth mode of semiconductor pentacene is obtained, which results in a large crystalline grain and good interface morphology at the channel/dielectric. Therefore, the mobility of Fe-OFET NVMs is greatly improved. As a result, a high performance flexible Fe-OFET NVM is achieved, with a low P/E voltage of ±15 V, high mobility up to 0.5 cm² V⁻¹ s⁻¹, reliable P/E endurance property over 1000 cycles, stable data storage retention capability over 6000 s, and excellent mechanical bending durability without visible degradation after 2000 repetitive tensile bending cycles at a small curvature radius of 4.0 mm.