A dual-mode secure UHF RFID tag with a crypto engine in 0.13-μm CMOS

An ultra-high-frequency (UHF) radio frequency identification (RFID) secure tag chip with a non-crypto mode and a crypto mode is presented. During the supply chain management, the tag works in the non-crypto mode in which the on-chip crypto engine is not enabled and the tag chip has a sensitivity of -12.8 dBm for long range communication. At the point of sales (POS), the tag will be switched to the crypto mode in order to protect the privacy of customers. In the crypto mode, an advanced encryption standard (AES) crypto engine is enabled and the sensitivity of the tag chip is switched to +2 dBm for short range communication, which is a method of physical protection. The tag chip is implemented and verified in a standard 0.13-μm CMOS process.     

An ultra-broadband distributed passive gate-pumped mixer in 0.18μm CMOS

A broadband distributed passive gate-pumped mixer(DPGM) using standard 0.18μm CMOS technology is presented.By employing distributed topology,the mixer can operate at a wide frequency range.In addition,a fourth-order low pass filter is applied to improve the port-to-port isolation.This paper also analyzes the impedance match and conversion loss of the mixer,which consumes zero dc power and exhibits a measured conversion loss of 9.4—17 dB from 3 to 40 GHz with a compact size of 0.78 mm~2.The input referred 1 dB compression point is higher than 4 dBm at a fixed IF frequency of 500 MHz and RF frequency of 23 GHz,and the measured RF-to-LO, RF-to-IF and LO-to-IF isolations are better than 21,38 and 45 dB,respectively.The mixer is suitable for WLAN, UWB,Wi-Max,automotive radar systems and other millimeter-wave radio applications.     

A dual mode UHF EPC Gen 2 RFID tag in 0.18 μm CMOS

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that the chip consumes 12 μW at 1 V supply voltage when it communicates with the reader. The chip is fabricated in 0.18 μm standard CMOS technology and occupies 0.95 mm² die area.     

An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags

This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

A low power voltage limiter for a full passive UHF RFID sensor on a 0.35 μm CMOS process

This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9 V with a voltage deviation of only ±0.065 V for the 12 measured dies. The measured current consumption is only 150 nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35 μm CMOS technology.     

A wideband current-commutating passive mixer for multi-standard receivers in a 0.18 μm CMOS

This paper reports a wideband passive mixer for direct conversion multi-standard receivers.A brief comparison between current-commutating passive mixers and active mixers is presented.The effect of source and load impedance on the linearity of a mixer is analyzed.Specially,the impact of the input impedance of the transimpedance amplifier(TIA),which acts as the load impedance of a mixer,is investigated in detail.The analysis is verified by a passive mixer implemented with 0.18 m CMOS technology.The circuit is inductorless and can operate over a broad frequency range.On wafer measurements show that,with radio frequency(RF) ranges from 700 MHz to 2.3 GHz,the mixer achieves 21 dB of conversion voltage gain with a-1 dB intermediate frequency(IF) bandwidth of 10 MHz.The measured IIP3 is 9 dBm and the measured double-sideband noise figure(NF) is 10.6 dB at 10 MHz output.The chip occupies an area of 0.19 mm2 and drains a current of 5.5 mA from a 1.8 V supply.     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

A reconfigurable passive mixer for multimode multistandard receivers in 0.18 μm CMOS

This paper presents a reconfigurable quadrature passive mixer for multimode multistandard receivers. By using controllable transconductor and transimpedance-amplifier stages, the voltage conversion gain of the mixer is reconfigured according to the requirement of the selected communication standard Other characteristics such as noises figure, linearity and power consumption are also reconfigured consequently. The design concept is verified by implementing a quadrature passive mixer in 0.18 μm CMOS technology. On wafer measurement results show that, with the input radio frequency ranges from 700 MHz to 2.3 GHz, the mixer achieves a controllable voltage conversion gain from 4 to 22 dB with a step size of 6 dB. The measured maximum ⅡP3 is 8.5 dBm and the minimum noise figure is 8.0 dB. The consumed current for a single branch (I or Q) ranges from 3.1 to 5.6 mA from a 1.8 V supply voltage. The chip occupies an area of 0.71 mm² including pads.     

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.     

A RF receiver frontend for SC-UWB in a 0.18-μm CMOS process

正A radio frequency(RF) receiver frontend for single-carrier ultra-wideband(SC-UWB) is presented. The front end employs direct-conversion architecture,and consists of a differential low noise amplifier(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The proposed LNA employs source inductively degenerated topology.First,the expression of input impedance matching bandwidth in terms of gate-source capacitance, resonant frequency and target S_(11) is given.Then,a noise figure optimization strategy under gain and power constraints is proposed,with consideration of the integrated gate inductor,the bond-wire inductance,and its variation.The LNA utilizes two stages with different resonant frequencies to acquire flat gain over the 7.1-8.1 GHz frequency band,and has two gain modes to obtain a higher receiver dynamic range.The mixer uses a double balanced Gilbert structure.The front end is fabricated in a TSMC 0.18-/im RF CMOS process and occupies an area of 1.43 mm~2.In high and low gain modes,the measured maximum conversion gain are 42 dB and 22 dB,input 1 dB compression points are -40 dBm and -20 dBm,and S_(11) is better than -18 dB and -14.5 dB.The 3 dB IF bandwidth is more than 500 MHz.The double sideband noise figure is 4.7 dB in high gain mode.The total power consumption is 65 mW from a 1.8 V supply.     

A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

A low cost fully integrated single-chip UHF radio frequency identification(RFID) reader SoC for short distance handheld applications is presented.The SoC integrates all building blocks—including an RF transceiver,a PLL frequency synthesizer,a digital baseband and an MCU—in a 0.18μm CMOS process.A high-linearity RX frontend is designed to handle the large self-interferer.A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader.The measure...     

A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process

The prolific growth of portable electronic devices (PED) has generated tremendous interests among researchers to develop programmable phase-locked loops (PLLs) because of their abilities to produce multiple spectrally pure output frequencies from a fixed frequency oscillator. The power consumption of the RF block of a PED is mostly dominated by the programmable PLLs which are widely used in the design of these devices. Therefore to reduce the overall power consumption in a portable device and to increase the battery life time, low-voltage and low-power are the two key requirements for the PLL design. In this work an improved programmable fractional frequency divider has been incorporated to enhance the overall performance of the PLL that includes lower operating supply voltage and lower power consumption compared to the state-of-art. The proposed programmable fractional PLL has an operating frequency in the range of 1.7–2.5 GHz, and a frequency resolution of 2.5 MHz. Measurement results reveal that the proposed programmable PLL can operate at 2.4 GHz with a 1.46 V power supply voltage and only 10 mW of power consumption.     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

Design and analysis of a UWB low-noise amplifier in the 0.18μm CMOS process

An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW （without output buffer for measurement） with a 1.8 V power supply and occupies 0.88 mm^2.     

A new current mode APS in 0.18 μm standard CMOS process for smart image sensors

In this paper we present a new current mode structure for active pixel sensor (APS) which is an essential part in fast parallel processing Smart CMOS Image Sensors such as wireless capsule endoscopy. Using two diodes (N+/P-Well and P-Well/Deep-N-Well) in parallel like a pinned photo-diode (PD) improves sensing of optical signal and thus leads to higher sensitivity than a conventional PD. Also integrated signal amplification inside the collection area of the pixel increases the sensitivity of the device due to the amplification in the pixel. The proposed structure with regards to using Deep-N-Well/P-Substrate junction as a guard ring, suppresses the pixel cross-talk highly. In pixel delta reset sampling helps to make feasible on-chip parallel processing. A test structure, consist of 8 × 8 pixels of the proposed current mode APS has been simulated by standard 0.18 μm RF-CMOS technology of TSMC with a 21 × 23 μm² pixel size. Fill factor of the pixel is 24 %.     

A curvature calibrated bandgap reference with base-emitter current compensating in a 0.13μm CMOS process

In bandgap references,the effect caused by the input offset of the operational amplifier can be effectively reduced by the utilization of cascade bipolar junction transistors(BJTs).But in modern CMOS logic processes,due to the small value ofβ,the base-emitter path of BJTs has a significant streaming effect on the collector current,which leads to a large temperature drift for the reference voltage.To solve this problem,a base-emitter current compensating technique is proposed in a cascade BJT bandgap refe...     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.