FPGA芯片最少配置的图论方法研究

国内外对于FPGA芯片最少配置的研究基本上是采取一种自底向上的方法。由于图论在电路分析中有着广泛的应用,因此,本文将图论的思想应用在FPGA最少配置的研究中,即将其内部的门单元看作图论中的点,将它们之间的连线看作图论中的线,采用了一种自顶向下的方法研究了CLB和IOB所需的最少配置次数。经过图论建模和图论的遍历分析,对于XC4000系列FPGA,得到CLB的最少配置次数为5次,IOB的最少配置次数为3次的结论。     

一种基于匹配理论的FPGA三级互连网络测试方法

针对FPGA中包含三级可编程开关的互连网络测试,该文提出了一种基于匹配理论的减少配置次数并且与阵列规模无关的测试方法。该方法通过建立结构测试图,按照图的道路长进行分块并应用最小覆盖和最大匹配的原理减少配置次数。对于不同的互连网络结构,与其它方法相比,该方法的配置次数至少减少了10%,并且与阵列规模无关。     

An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family

This paper describes an approach to minimize the number of test configurations for testing the logic cells of a RAM-based FPGA taking into account the configurability of such flexible device. The proposed approach concerns the XILINX 4000 family. On this example of FPGA, a bottom-up test technique is first used to generate test configurations for the elementary modules, then test configurations for a single logic cell, and finally test configurations for the m × m array of logic cells. In this bottom-up technique, it is shown that the key point is the minimization of the number of test configurations for a logic cell. An approach for the logic cell of the XILINX4000 family is then described to define a minimum number of test configurations knowing the test configurations of its logic modules. This approach gives only 5 test configurations for the XILINX4000 family while the previous published works concerning Boolean testing of this FPGA family gives 8 or 21 test configurations.     

极大平面图的结构与着色理论(2)多米诺构形与扩缩运算

业已证明四色猜想的数学证明可归结为刻画4-色漏斗型伪唯一4-色极大平面图的特征。为刻画此类极大平面图的结构特征,本文提出一种构造极大平面图的方法 扩缩运算。研究发现:此方法的关键问题是需要清楚一种构形,称为多米诺构形。文中构造性地给出了多米诺构形的充要条件;在此基础上提出并建立了一个图的祖先图与子孙图理论与构造方法。特别证明了:任一最小度4的n(9)-阶极大平面图必含(n-2)-阶或(n-3)-阶祖先图;给出极大平面图的递推构造法,并用此方法构造出6~12-阶所有最小度的4极大平面图。扩缩运算是本系列文章的基石。     

基于FPGA的图着色问题求解

图着色问题是在满足相邻顶点不能分配相同颜色且颜色数最少的约束条件下,将图的顶点划分为不相交的集合,且每个集合中的顶点分配相同的颜色。由于图着色问题属于NP-完全问题,求解图着色问题的算法复杂度会随顶点个数的增加呈指数级增长。当顶点个数非常大时,通用处理器求解图着色问题的性能将会显著下降。因此,该文基于现场可编程逻辑门阵列(FPGA)实现求解图着色算法的专用硬件加速器。首先依据FPGA模块化的设计思路提出并实现了基于回溯法的图着色问题求解的硬件架构;其次分析了FPGA内部消耗资源与图着色顶点数之间的关系;最后利用通用异步收发传输器协议实现了通用处理器与FPGA的通信。实验结果表明,相比于在通用处理器上利用软件实现图着色算法,基于FPGA所实现的图着色算法运行时间减少了一个数量级。除此之外,FPGA内部消耗资源数与顶点个数呈线性关系,且每次迭代时FPGA运算所消耗的时间与顶点个数无关。     

Fine-grained and coarse-grained behavioral partitioning witheffective utilization of memory and design space exploration formulti-FPGA architectures

Reconfigurable computers (RCs) host multiple field programmable gate arrays (FPGAs) and one or more physical memories that communicate through an interconnection fabric. State-of-the-art RCs provide abundant hardware and storage resources, but have tight constraints on FPGA pin-out and inter-FPGA interconnection resources. These stringent constraints are the primary impediment for multi-FPGA partitioning tools to generate high-quality designs, in this paper, we present two integrated partitioning and synthesis approaches for RCs. The first approach involves fine-grained partitioning of a scheduled data-flow graph (DFG, or an operation graph), and the second involves a coarse-grained partitioning of an unscheduled control data flow graph (CDFG, or a block graph). A hardware design space exploration engine is integrated with the block graph partitioner that dynamically contemplates multiple schedules during partitioning. The novel feature in the partitioning approaches is that the physical memory in the RC is effectively used to alleviate the FPGA pin-out and inter-FPGA interconnection bottle-neck. Several experiments have been conducted, targeting commercial multi-FPGA boards, to compare the two partitioning approaches, and detailed summaries are presented     

Analysis of Fourth-Order DC–DC Converters: A Flow Graph Approach

The signal flow graph (SFG) nonlinear modeling approach is well known for modeling DC-DC converters and it is a powerful analysis tool for higher order converter systems. Modeling of several specific fourth-order DC-DC converter circuits have been reported using conventional state-space averaging. Particular emphasis has been given, so far, only to arrive at any of the large, small-signal (SS) and steady-state models but not a generalized one. This paper gives the generalized SFG model of the fourth-order DC-DC converter topology that is useful for generating different types of fourth-order DC-DC converter circuits unified models. Further, it is shown that the deduction of large, SS and steady-state models from these unified SFGs is easy and straightforward. All possible fourth-order DC-DC converter circuits from its generalized topology have been identified and an analysis of a few converter circuits is given here for illustration of the proposed modeling method. Large-signal (LS) models are developed for different topology configurations and are programmed in SIMULINK simulator. LS responses against supply and load disturbances are obtained. Experimental observations are provided to validate the proposed modeling method.     

FPGA最小系统的数字电源设计

文章介绍了一种FPGA最小系统的数字电源设计方法。FPGA最小系统的数字电源包括FPGA端口电压、内核电压、EEPROM配置芯片内核电压等部分。对数字电源产生、软启动、上电时序控制进行了设计改进,可以有效避免数字电源设计不合理造成的FPGA最小系统工作不稳定的设计隐患,对于稳定可靠的FPGA最小系统设计具有重要意义。     

Geometrical considerations in realization of cut-set matrices into graphs †

A practical method is described for testing whether a given matrix can be realized as a graph or not. The method is based on one's geometrical intuition in seeing whether or not certain configurations can be drawn in plane and the test can be carried out evon by an unskilled person.     

攻击图的网络威胁自动建模方法研究

为了增强网络的安全性,对网络整体进行威胁分析和评估应用,结合攻击图的特点,研究并提出了一种攻击图的网络威胁自动化建模方法。在攻击图生成之前,抽象出网络威胁数学模型,包括主机信息、拓扑信息、漏洞信息和攻击者信息四个组成部分。并针对所建的网络威胁模型提出自动建模方法和具体的自动化流程。基于此,结合攻击事件的Büchi模型和CTL描述,使用符号模型检验算法自动生成攻击图,为攻击图的应用奠定基础。     

Multicluster tools scheduling: an integrated event graph and network model approach

Steady-state throughput and scheduling of a multicluster tool become complex as the number of modules and clusters grows. We propose a new methodology integrating event graph and network models to study the scheduling and throughput of multicluster tools. A symbolic decision-move-done graph modeling is developed to simplify discrete-event dynamics for the multicluster tool. This event graph is further used for searching feasible action sequences of the cluster tool. By representing sequences with networks, an extended critical path method is applied to calculate the corresponding cycle time. Grouping methods that are based on network are also introduced to reduce the searching complexity. Compared with optimization-based scheduling approaches, the proposed methodology can directly capture the cyclic characteristic of cluster tool schedules and be applied to analyze the impact of process and wafer flow variations on cycle time and robot schedules. We have successfully applied this new methodology to dozens of cluster tools at Intel Corporation. A chemical-mechanical planarization polisher is employed as an example to illustrate and validate the proposed methodology.     

A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration

The ever increasing adoption of field programmable devices in various application domains for building complex embedded systems based on FPGA processors along with the reliability issues having emerged for FPGA devices built with the latest nanometer technologies, have raised the need for new fault tolerant techniques in order to improve dependability and extend system lifetime. In addition, the runtime partial reconfiguration technology highly mature in the modern FPGA families along with the availability of unused programmable resources in most FPGA designs provide new and interesting opportunities to build advanced fault tolerance mechanisms. In this paper, we exploit the dynamic reconfiguration potential of today’s FPGA architectures and the advances in the related design support tools and we propose a fault-tolerant approach for FPGA embedded processors based on runtime partial reconfiguration. According to the proposed methodology, the processor core is partitioned into reconfigurable modules and each module is duplicated to implement a concurrent error detection mechanism. Precompiled configurations containing spare resources are generated for each duplicated module and are used to repair at runtime the defective modules. Also, a fault tolerance scheme for the proxy logic of the reconfigurable modules, which cannot move in the alternative configurations along with the rest logic, is proposed. Moreover, a compression method for the alternative partial bitstreams, which significantly reduces the high storage space requirements of the proposed approach, is presented. Two different hardware decompression schemes have been implemented in a Virtex-5 device and compared in terms of area overhead and decompression latency. Furthermore, a thorough examination has been performed, regarding how the percentage of the spare resources and their allocation in the reconfigurable regions affect the compression efficiency and the processor performance. Finally, the proposed approach has been demonstrated in three different components – ALU, multiplier-accumulator, and instruction-fetch unit – of an open-source embedded processor.     

视频格式转换资源最小FPGA解决方案

提供了对隔行数字视频进行去隔行,帧频转换,分辨率变换的最简FPGA设计方案.达到FPGA内部资源和外部RAM耗用量都为最小的目的.该方案通过一对乒乓工作的RAM将去隔行,帧频转换,分辨率变换这三项本需分级完成的处理同时实现,使得资源耗用得以最小化.其中去隔行采用场合并方式,帧频转换采用帧重复方式,分辨率变换采用均匀插值方式.     

Xilinx FPGA上电时序分析与设计

提出了由于FPGA容量的攀升和配置时间的加长,采用常规设计会导致系统功能失效的观点.通过详细描述Xilinx FPGA各种配置方式及其在电路设计中的优缺点,深入分析了FPGA上电时的配置步骤和工作时序以及各阶段I/O管脚状态,说明了FPGA上电配置对电路功能的严重影响,最后针对不同功能需求的FPGA外围电路提出了有效的设计建议.     

Reconstructing Extended Perfect Binary One-Error-Correcting Codes From Their Minimum Distance Graphs

The minimum distance graph of a code has the codewords as vertices and edges exactly when the Hamming distance between two codewords equals the minimum distance of the code. A constructive proof for reconstructibility of an extended perfect binary one-error-correcting code from its minimum distance graph is presented. Consequently, inequivalent such codes have nonisomorphic minimum distance graphs. Moreover, it is shown that the automorphism group of a minimum distance graph is isomorphic to that of the corresponding code.      

基于FPGA和LMS算法的系统建模

自适应滤波器用于实现对未知系统的建模,用Matlab中的Simulink对LMS算法的实现方法进行仿真,在FP—GA中实现了LMS算法及其建模,并对FPGA设计的系统建模结果采用Matlab软件仿真,以增强Quartus的仿真功能,从而得到完整且直观的仿真结果。这种系统建模所采用的仿真、实现和验证方法同样适用于消除宽带信号中的窄带干扰,实现自适应谱线增强以及自适应均衡等,具有一定通用性。     

The finite-element modeling of three-dimensional electromagneticfields using edge and nodal elements

An efficient and accurate finite-element method is presented for computing transient as well as time-harmonic electromagnetic fields in three-dimensional configurations containing arbitrarily inhomogeneous media that may be anisotropic. To obtain accurate results with an optimum computational efficiency, both consistently linear edge and consistently linear nodal elements are used for approximating the spatial distribution of the field. Compared with earlier work, the formulation is generalized by adding a method for explicitly modeling the normal continuity along interfaces that are free of surface charge. In addition, the conditions for efficiently solving time-harmonic problems using a code designed for solving transient problems are discussed. A general and simple method for implementing arbitrary inhomogeneous absorbing boundary conditions for modeling arbitrary incident fields is introduced     

Automatic Synthesis of Motion Estimation Processors Based on a New Class of Hardware Architectures

A new class of fully parameterizable multiple array architectures for motion estimation in video sequences based on the Full-Search Block-Matching algorithm is proposed in this paper. This class is based on a new and efficient AB2 single array architecture with minimum latency, maximum throughput and full utilization of the hardware resources. It provides the ability to configure the target processor within the boundary values imposed for the configuration parameters concerning the algorithm setup, the processing time and the circuit area. With this purpose, a software configuration tool has been implemented to determine the set of possible configurations which fulfill the requisites of a given video coder. Experimental results using both FPGA and ASIC technologies are presented. In particular, the implementation of a single array processor configuration on a single-chip is illustrated, evidencing the ability to estimate motion vectors in real-time.     

The FE-BIE technique applied to some 2-D problems relevant toelectromagnetic compatibility: optimal choice of mechanisms to take intoaccount periodicity

A study of mechanisms to account for periodicity when modeling two-dimensional (2-D) structures with a hybrid finite-element boundary integral equation (FE-BIE) method is presented. These techniques are either based on the use of Green's functions or on the application of the Floquet-Bloch theorem as a periodic boundary condition. The described formalism can be used to model very diverse problem geometries as is demonstrated by means of some typical examples. For these configurations, it is shown how an optimal choice can be made between the mechanisms that impose periodicity