Study and modeling of the transport mechanism in a Schottky diode on the basis of a GaAs semiinsulator

The current through a metal-semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode: diffusion of the semiconductor carriers in metal, thermionic emission-diffusion (TED) of carriers through a Schottky gate, and a mechanical quantum that pierces a tunnel through the gate. The system was solved by using a coupled Poisson-Boltzmann algorithm. Schottky BH is defined as the difference in energy between the Fermi level and the metal band carrier majority of the metal-semiconductor junction to the semiconductor contacts. The insulating layer converts the MS device in an MIS device and has a strong influence on its current-voltage (I-V) and the parameters of a Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behaviour of Schottky diodes with and without an interfacial insulator layer. These include the particular distribution of interface states, the series resistance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase in the process of thermionic electrons and holes, which will in turn act on the I-V characteristic of the diode, and an overflow maximum value [NT = 3 × 10²⁰] is obtained. The I-V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.     

Simulation of Schottky barrier MOSFETs with a coupled quantuminjection/Monte Carlo technique

A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 μm Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 Å gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage     

Optically-controlled ion-implanted GaAs MESFET characteristic withopaque gate

An analytical modelling has been carried out for an ion-implanted GaAs MESFET having a Schottky gate opaque to incident radiation. The radiation is absorbed in the device through the spacings of source, gate, and drain unlike the other model where gate is transparent/semitransparent. Continuity equations have been solved for the excess carriers generated in the neutral active region, the extended gate depletion region and the depletion region of active (n) and substrate (p) junction. The photovoltage across the channel and the p-layer junction and that across the Schottky junction due to generation in the arc region of the gate depletion layer are the two important controlling parameters. The I-V characteristics and the transconductance of the device have been evaluated and discussed     

Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses

The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this.     

Physical identification of gate metal interdiffusion in GaAs PHEMTs

The Ti metal interdiffusion of Ti/Pt/Au gate metal stacks in 0.15-/spl mu/m GaAs PHEMTs subjected to high-temperature accelerated lifetest has been physically identified using scanning transmission electron microscopy. Further energy dispersive analysis with X-ray (EDX) analysis confirms the Ti diffusion into the AlGaAs Schottky barrier layer and the decrease of Schottky barrier height suggests the Ti-AlGaAs intermetallic formation, which is consistent with previous Rutherford backscattering spectroscopy/X-ray photoelectron spectroscopy studies. The Ti metal interdiffusion reduces the separation of the gate metal and InGaAs channel, thus leading to a slight Gm increase, positive shift in pinchoff voltage, and S21 increase during the preliminary portion of the lifetest. Accordingly, the Ti interdiffusion effect implies that the lifetime of GaAs PHEMTs subjected to high-temperature accelerated lifetest could be dependent upon the initial thickness of the Schottky layer underneath the gate metal.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

Annealing before gate metal deposition related noise performance in AlGaN/GaN HEMTs

For a further improvement of the noise performance in AlGaN/GaN HEMTs, reducing the relatively high gate leakage current is a key issue. In this paper, an experiment was carried out to demonstrate that one method during the device fabrication process can lower the noise. Two samples were treated differently after gate recess etching: one sample was annealed before metal deposition and the other sample was left as it is. From a comparison of their Ig-Vg characteristics, a conclusion could be drawn that the annealing can effectively reduce the gate leakage current. The etching plasma-induced damage removal or reduction after annealing is considered to be the main factor responsible for it. Evidence is given to prove that annealing can increase the Schottky barrier height. A noise model was used to verify that the annealing of the gate recess before the metal deposition is really effective to improve the noise performance of AlGaN/GaN HEMTs.     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

表面处理与离子注入对GaN HEMT肖特基特性的影响

研究了不同的表面处理方法及离子注入对AlGaN/GaN HEMT肖特基特性的影响.在栅金属化前,采用不同的表面处理方法进行实验,发现通过表面处理,栅肖特基特性得到一定的改善,但还不能从根本上解决漏电大、理想因子偏高的问题.进一步实验发现,硼离子注入才是导致栅肖特基特性变差的主要因素,通过对离子注入的优化,器件栅金属化后的理想因子减小到1.6,栅源反向电压为-20 V时,反向泄漏电流为2.8×10-6 A.     

Theoretical analysis of the quantum photoelectric yield in Schottky diodes

A detailed analytical calculation of the photoelectric quantum yield in Schottky diodes is presented. The transport of carriers in the surface space charge region is treated explicitly, taking account of photogeneration, diffusion and drift in the non-uniform electric field. Boundary conditions at the interface are expressed in terms of surface recombination velocity and emission velocity of excess carriers into the metal.It is shown that the metal-semiconductor interface strongly affects the collection efficiency of short wavelength generated electron-hole pairs. This effect basically originates in the emission flux of majority carriers into the metal.Current, charge carriers distributions and quantum yields are computed using the data of AuCdTe Schottky barriers.     

Gate controlled 2-DEG varactor for VCO applications in microwave circuits

A novel gate controlled Schottky diode varactor is introduced. The three-terminal varactor is a modulation-doped heterostructure of AlGaAs/GaAs with two Schottky contacts, similar to a metal–semiconductor–metal (MSM) diode. Schottky metal contacts are made to a two-dimensional electron gas (2-DEG). The third contact, the gate contact is formed from highly doped n⁺ GaAs material to allow an open optical window that can be used for optical gating and mixing. Structure capacitance is less than 1 PF and a change of more than 30% from the zero bias capacitance is observed with the applied gate voltage. On the basis of our quasi two-dimensional C–V model, the layer structure and device dimensions can be optimized and scaled to cover a wide range of operations in the microwave and millimeter wave regimes.     

A new type of Schottky tunnel transistor

A new type of tunnel transistor, in which electrons can tunnel through a very thin Schottky barrier between an n⁺- accumulation-layer formed just under a MOS gate for controlling the tunneling current and the Schottky metal, is proposed and demonstrated. This tunnel transistor has no threshold voltage in cathode current I_k vs. cathode voltage V_k curves. Theoretical calculations based on Stratton's tunneling theory are carried out and have trends similar to the experimental results     

SiC肖特基栅JFET功率特性的研究

提出了一种新型结构的SiC结型场效应晶体管,采用肖特基接触替代P+型栅区,以降低SiC JFET的工艺复杂度,并提高器件的功率特性。建立了器件的数值模型,对不同材料和结构参数下的功率特性进行了仿真。结果表明,与PN结栅相比,肖特基栅结构可以有效降低SiC JFET的开态电阻;与常规结构的双极模式SiC JFET相比,在SiC肖特基栅JFET的栅极正偏注入载流子,同样可以有效降低器件的开态电阻,折中器件的正反向特性,但不会延长开关时间。     

HfO_2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在 p- Si(1 0 0 )衬底上制备了 Hf O2 栅介质层 ,研究了 Hf O2 高 k栅介质的电流传输机制和应力引起泄漏电流 (SIL C)效应 .对 Hf O2 栅介质泄漏电流输运机制的分析表明 ,在电子由衬底注入的情况下 ,泄漏电流主要由 Schottky发射机制引起 ,而在电子由栅注入的情况下 ,泄漏电流由 Schottky发射和 Frenkel-Poole发射两种机制共同引起 .通过对 SIL C的分析 ,在没有加应力前 Hf O2 / Si界面层存在较少的界面陷阱 ,而加上负的栅压应力后在界面处会产生新的界面陷阱 ,随着新产生界面陷阱的增多 ,这时在衬底注入的情况下 ,电流传     

Simplified ohmic and Schottky contact formation for field effecttransistors using the single layer integrated metal field effecttransistor (SLIMFET) process

A new III-V semiconductor device fabrication process for GaAs-based field effect transistors (FET) is presented which uses a single lithographic process and metal deposition step to form both the ohmic drain/source contacts and the Schottky gate contact concurrently. This single layer integrated metal FET (SLIMFET) process simplifies the fabrication process by eliminating an additional lithographic step for gate definition, a separate gate metallization step, and thermal annealing for ohmic contact formation. The SLIMFET process requires a FET structure which incorporates a compositionally graded In_xGa_1-xAs cap layer to form low resistance, nonalloyed ohmic contacts using standard Schottky metals. The SLIMFET process also uses a Si₃N₄ mask to provide selective removal of the InGaAs ohmic layers from the gate region prior to metallization without requiring an additional lithographic step. GaAs MESFET devices were fabricated using this new SLIMFET process which achieved DC and RF performance comparable to GaAs MESFET's fabricated by conventional methods     

Decrease in on-state gate current of AlGaN/GaN HEMTs by recombination-enhanced defect reaction of generated hot carriers investigated by TCAD simulation

Changes in the on-state gate current of AlGaN/GaN high-electron-mobility transistors (HEMTs) under various electrical and thermal stress conditions have been analyzed by technology computer-aided design (TCAD) simulation. A larger gate current is observed under on-state bias condition than that under off-state bias condition. The TCAD simulation indicates that on-state gate current flows from the heated gate electrode to the AlGaN layer by tunneling or hopping through the gate depletion layer when we apply some deep-donor-type traps under the gate in the AlGaN barrier layer. The gate current is caused by electrons that flow and is pulled away by the applied gate-to-drain voltage under a high channel temperature condition. The deep traps benefit both the on- and off-state gate current behavior. We found that the on-state gate current is effectively decreased by electrical stress under the on-state condition. Electroluminescence measurement indicates that a large number of hot carriers are generated under this condition. The results suggest that the process-induced crystal defects are annealed out by non-radiative recombination of the generated hot carriers by a recombination-enhanced defect reaction mechanism. The change in the on-state gate current in the TCAD simulation can be successfully explained by the decrease in the donor traps.     

Inverted gate GaAs MESFET by epitaxial liftoff

A GaAs film deposited on metal by epitaxial liftoff can form a Schottky barrier. This film is used to make a 1 mu m gate length inverted gate GaAs metal-semiconductor field-effect transistor (MESFET) that can be pinched off by the inverted gate.<>     

Characterisation of a Schottky ISFET as Hg-MOSFET and as cytochrome P450-ENFET

A cost-effective and simple method is proposed wherein a Schottky ion sensitive field effect transistor (Schottky ISFET)-based sensor is characterised as metal oxide semiconductor and enzyme field effect transistor (ENFET). This technique involves deposition of mercury (Hg) as gate material over the sensing layer mitigating the complexity of fabrication process, thereby eliminating the need of refabricating an identical device. A Schottky-based ISFET simplifies the fabrication process as the requisite for doping of source and drain regions becomes redundant. Steps involved in lithography process for fabricating metal oxide semiconductor field effect transistor (MOSFET) are reduced with the use of liquid metal Hg as gate over layer. Such a device can be transformed back to an ISFET without any additional etching process. Furthermore, the same ISFET device can be utilised as an ENFET when the former is used in conjunction with a biological element. In this work, a Schottky-based ISFET has been characterised as Hg-MOSFET and as cytochrome P450-ENFET. Multiple tests on the device exhibit that the same ISFET sensor can be used both as a MOSFET and an ENFET with good repeatability and versatility without losing its sensitivity.     

Effect of Gate Sinking on the Device Performance of the InGaP/AlGaAs/InGaAs Enhancement-Mode PHEMT

An enhancement-mode InGaP/AlGaAs/InGaAs pseudomorphic high-electron mobility transistor using platinum (Pt) as the Schottky contact metal was investigated for the first time. Following the Pt/Ti/Pt/Au gate metal deposition, the devices were thermally annealed at 325 degC for gate sinking. After the annealing, the device showed a positive threshold voltage (V_th) shift from 0.17 to 0.41 V and a very low drain leakage current from 1.56 to 0.16 muA/mm. These improvements are attributed to the Schottky barrier height increase and the decrease of the gate-to-channel distance as Pt sinks into the InGaP Schottky layer during gate-sinking process. The shift in the V_th was very uniform across a 4-in wafer and was reproducible from wafer to wafer. The device also showed excellent RF power performance after the gate-sinking process     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.