静电放电作用下微波双极型晶体管的失效机理研究

通过理论建模和试验测试的方法研究了多指结构微波双极型晶体管在静电放电作用下的热稳定性和电稳定性。选择2SC3356作为受试器件,对100个测试样本进行人体模型静电放电注入实验,并从器件内部电场强度、电流密度和温度分布变化出发,用二维器件级仿真软件辅助分析了在静电放电应力下其内在损伤过程与机理。由于指间热耦合的存在,雪崩电流在各指上分布不均,局部的电流拥挤和过热效应会导致晶格损伤。试验结果表明,由于特殊的物理结构,受试器件对静电放电最敏感的端对并不是EB结,而是CB结,当静电放电电压增大到1.3KV时,CB结首先损坏。失效分析进一步表明静电放电引起的失效机理通常是介质层的击穿和局部铝硅共晶体的过热融化。静电放电注入实验的过程中存在积累效应,多次低强度的注入测试会导致潜在性失效并使器件性能大幅下降。     

Modelling of thermal failure of metallic interconnects under electrostatic discharge transients

Temperature dependence of metal electrical resistivity is taken into account in modelling of thermal failure of metallic interconnects under electrostatic discharge (ESD) events. SPICE-based electro-thermal modelling is used to calculate the maximum temperature rise in the interconnect during stress. New ESD design guidelines for interconnects, based on the threshold temperature of latent failure, are proposed to optimise the interconnect width.     

高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究

提高射频功率器件的鲁棒性有利于增强器件的抗静电放电能力和抗失配能力.为了直观地了解器件内部发生的电学过程，本文研究了高鲁棒性N型沟道RF-LDMOS（Radio Frequency Lateral Diffusion MOS）在TLP（Transmission Line Pulse）应力下的电学机理.利用0.18μm BCD（Bipolar/CMOS/DMOS）先进制程，实现了特定尺寸器件的设计与流片.通过实测与仿真的对比，发现静电放电失效的随机性、芯片内部的热效应是导致仿真和实测差异的非理想因素.通过对TLP仿真的各阶段重要节点的分析，证明了源极下方的P型埋层有利于提高空穴电流的泄放能力，从而提高RF-LDMOS的鲁棒性.     

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-m CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the power-on reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.     

Hot-electron reliability and ESD latent damage

The impact of noncatastrophic electrostatic discharge (ESD) stress on hot-electron reliability as well as the effect of hot-electron (HE) injection on the ESD protection threshold are discussed. It is found that there is a factor-of-two-to-four deterioration in hot-electron reliability after low-level ESD stress. These two effects can be viewed as similar although HE is a low-current long-time process and ESD is a high-current short-time process. Therefore, techniques for characterizing hot-electron degradation were applied to measure quantitatively the damage due to ESD stress. This technique showed electrical evidence of current filaments during an ESD discharge     

Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method

Current distribution in vertical double-diffused MOS (DMOS) transistors of a Smart Power Technology are investigated under high current, short duration operation conditions by means of a backside laser interferometric thermal mapping technique. DMOS devices of different areas are studied under pulsed gate forward operation mode and under electrostatic discharge (ESD)-like stress with floating and grounded gate. The internal behavior of the devices observed by thermal mapping under these stress conditions is correlated with the electrical characteristics.     

Wavelength shifts of 1.5-μm DFB lasers due to human-body-modelelectrostatic discharge followed by accelerated aging experiments

This paper reports human-body-model (HBM) electrostatic discharge (ESD)-induced wavelength shifts of 1.5 μm InGaAsP/InP distributed feedback (DFB) lasers. Reverse-bias ESD has been exposed to the lasers. Their electrical and optical characteristics are significantly changed after ESD exposure. From most of ESD stressed lasers, the wavelength shifts are measured to be less than 2 Å. Subsequent aging results show that the aging-induced wavelength shifts of ESD damaged lasers are less than 0.5 Å. No significant impact on reliability has been found from ESD damaged lasers. Similar results are obtained from non-ESD damaged lasers except for the shift direction of the lasing wavelengths     

Analysis of the electrical breakdown in hydrogenated amorphoussilicon thin-film transistors

Electrical breakdown induced by systematic electrostatic discharge (ESD) stress of thin-film transistors used as switches in active matrix addressed liquid crystal displays has been studied using electrical measurements, electrical simulations, electrothermal simulations, and postbreakdown observations. Breakdown due to very short pulses (up to 1 μs) shows a clear dependence on the channel length. A hypothesis that electrical breakdown in the case of short channel TFTs is due to the punch-through is built on this dependence and is proved by means of electrical simulations. Further, the presence of avalanche breakdown in amorphous silicon thin-film transistors is simulated and confirmed. It is finally assumed that the breakdown is a thermal process. Three-dimensional (3-D) electrothermal simulations are performed in the static and transient regime, confirming the location of the breakdown spot within the TFT from the electrical simulations and postbreakdown observations     

Simulation of electrical overstress thermal failures in integratedcircuits

Electrical overstress (EOS) and electrostatic discharge (ESD) pose the most dominant threats to integrated circuits (ICs) reliability. As a measure for EOS/ESD reliability, the power-to-failure versus time-to-failure relationship (power profile) has been recently proposed to determine the EOS failure thresholds of integrated circuits. This paper presents a nonlinear mixed 2D-1D thermal simulator, iTSIM, for ESD/EOS failure studies in ICs. iTSIM's computational efficiency to handle large-scale EOS thermal problems in ICs derives from the special set of boundary conditions introduced in this paper. Simulated power profiles for various combinations of major thermal parameters of the IC die-package structure are shown to agree with experimental data     

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

A new silicon controlled rectifier (SCR)-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance is proposed. The circuit function to detect positive or negative electrical transients during system-level electrostatic discharge (ESD) and electrical fast transient (EFT) tests has been verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the new proposed detection circuit can successfully memorize the occurrence of system-level electrical transient disturbance events. The detection results can be cooperated with firmware design to execute system recovery procedures, therefore the immunity of microelectronic systems against system-level ESD or EFT tests can be effectively improved.     

一个LVTSCR并联PMOS的高维持电压ESD防护器件

为了在5 V片上输入输出端进行静电放电(ESD)防护,提出了一种新型的LVTSCR结构。使用Silvaco 2D TCAD软件对此器件进行包含电学及热学特性的仿真。此新型器件交换了LVTSCR中N-Well的N+、P+掺杂区并引入了一个类PMOS结构用来在LVTSCR工作前释放ESD电流。器件仿真结果显示,与LVTSCR相比,该器件获得了更高的维持电压(10.51 V),以及更高的开启速度(1.05×10-10 s),同时触发电压仅仅从12.45 V增加到15.35 V。并且,如果加入的PMOS结构选择与NMOS相同的沟道长度,器件不会引起热失效问题。     

ESD-induced degradation of vertical-cavity surface-emitting lasers

The sensitivity of proton implanted, vertical-cavity surface emitting lasers (VCSELs) to electrostatic discharge (ESD) pulses is investigated under human body model test conditions. Rather low degradation threshold pulse amplitudes were observed in forward bias (+1500 V) as well as reverse bias (-800 V) step stress tests. Monitoring both the electrical and optical parameters of the VCSELs during ESD stress, it was found that in forward bias ESD stress tests the optical degradation precedes the electrical degradation     

Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard

A hardware/firmware co-design solution in an 8-bits microcontroller has been proposed to practically fix the system-level electrostatic discharge (ESD) issue on the keyboard products. By including the especial ESD sensors and an additional ESD flag into the chip, the fast electrical transient due to the system-level ESD zapping on the keyboard can be detected. The firmware stored in the ROM of the 8-bits microcontroller is designed to automatically check the ESD flag to monitor the abnormal conditions in system operations. If the keyboard is upset or locked up by a system-level ESD transient, the microcontroller can be quickly recovered to a known and stable state. The 8-bits microcontroller with such a hardware/firmware co-design solution has been fabricated in a 0.45-μm CMOS process. The system-level ESD susceptibility of the keyboard with this 8-bits microcontroller has been improved from the original ±2 kV (±4 kV) to become greater than ±8 kV (±15 kV) in the contact-discharge (air-discharge) ESD zapping.     

Short-timescale thermal mapping of semiconductor devices

We report spatial mapping of temperature fields in semiconductor devices with sub-microsecond temporal resolution. The measurements are performed at a facility that integrates scanning laser-reflectance thermometry with electrical stressing capability. Data for SOI LDMOS transistors investigate transient heat diffusion within the buried silicon dioxide and capture large temperature gradients in the drift region, which result from the spatially-varying impurity concentration. The new thermometry facility is promising for the study of transistor and interconnect thermal failure due to electrostatic discharge (ESD)     

Electrostatic discharge in semiconductor devices: an overview

Electrostatic discharge (ESD) is an event that sends current through an integrated circuit (IC). This paper reviews the impact of ESD on the IC industry and details the four stages of an ESD event: (1) charge generation, (2) charge transfer, (3) device response, and (4) device failure. Topics reviewed are charge generation mechanisms, models for ESD charge transfer, electrical conduction mechanisms, and device damage mechanisms leading to circuit failure     

深槽TVS研究

以静电放电（ESD）以及其他一些电压浪涌形式随机出现的瞬态电压,通常存在于各种电子器件中。随着半导体器件日益趋向小型化、高密度和多功能。电子器件越来越容易受到电压浪涌的影响,甚至导致致命的伤害。从静电放电到闪电等各种电压浪涌都能诱导瞬态电流尖峰,瞬态电压抑制器（TVS）通常用来保护敏感电路受到浪涌的冲击。基于不同的应用。瞬态电压抑制器可以通过改变浪涌放电通路和自身的箝位电压来起到电路保护作用。为了节省芯片面积,并且获得更高的抗浪涌能力,深槽TVS的概念已经被提出和研究。深槽TVS的结面形成于纵向的深槽的侧壁,这样,在相同的芯片面积下,它有更多的有效结面积,即更强的放电能力。我们也可以预见,深槽TVS的小封装尺寸对应用于保护高端IC非常关键。     

NMOS器件ESD特性模拟

NMOS管I-V曲线在ESD(electrostatic discharges)脉冲电流作用下呈现出反转特性,其维持电压VH、维持电流IH、触发电压VB、触发电流IB以及二次击穿电流等参数将会影响NMOS管器件的抗ESD能力。文章通过采用SILVACO软件,对1.0μm工艺不同沟长和工艺条件的NMOS管静电放电时的峰值电场、晶格温度以及VH进行了模拟和分析。模拟发现,在ESD触发时,增加ESD注入工艺将使结峰值场强增强,VH减小、VB减小,晶格温度降低;器件沟长和触发电压VB具有明显正相关特性,但对VH基本无影响。最后分析认为NMOS管ESD失效主要表现为高电流引起的热失效,而电场击穿引起的介质失效是次要的。     

Frequency-Domain Measurement Method for the Analysis of ESD Generators and Coupling

A method for analyzing electrostatic discharge (ESD) generators and coupling to equipment under test in the frequency domain is proposed. In ESD generators, the pulses are excited by the voltage collapse across relay contacts. The voltage collapse is replaced by one port of a vector network analyer (VNA). All the discrete and structural elements that form the ESD current pulse and the transient fields are excited by the VNA as if they were excited by the voltage collapse. In such a way, the method allows analyzing the current and field-driven linear coupling without having to discharge an ESD generator, eliminating the risk to the circuit and allowing the use of the wider dynamic range of a network analyzer relative to a real-time oscilloscope. The method is applicable to other voltage-collapse-driven tests, such as electrical fast transient, ultrawideband susceptibility testing but requires a linear coupling path.     

Human body model electrostatic discharge tester using metal oxide semiconductor-controlled thyristors

Electrostatic discharge (ESD) testing for human body model tests is an essential part of the reliability evaluation of electronic/electrical devices and components. However, global environmental concerns have called for the need to replace the mercury-wetted relay switches, which have been used in ESD testers. Therefore, herein, we propose an ESD tester using metal oxide semiconductor-controlled thyristor (MCT) devices with a significantly higher rising rate of anode current (di/dt) characteristics. These MCTs, which have a breakdown voltage beyond 3000 V, were developed through an in-house foundry. As a replacement for the existing mercury relays, the proposed ESD tester with the developed MCT satisfies all the requirements stipulated in the JS-001 standard for conditions at or below 2000 V. Moreover, unlike traditional relays, the proposed ESD tester does not generate resonance; therefore, no additional circuitry is required for resonant removal. To the best of our knowledge, the proposed ESD tester is the first study to meet the JS-001 specification by applying a new switch instead of an existing mercury-wetted relay.     

Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (V_t) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (V_h) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the V_t of the proposed circuit increased from 14 V to 27.8 V, and V_h increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V.