CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed in this paper. The proposed VGA uses the differential-ramp based technique, digitally programmable gain amplifier (PGA) can be converted to analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous time feedback that includes Miller effect and linear rang operation MOS transistor to realize large value capacitor and resistor to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in SMIC 0.13 m CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A programmable gain amplifier with a DC offset calibration loop for a direct-conversion WLAN transceiver

A high-linearity PGA (Programmable Gain Amplifier) with DC offset calibration loop is proposed in this paper. The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity. A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem. This PGA is fabricated in TSMC 0.13um CMOS technology. The measurements show that the receiver PGA （RXPGA）provides 64dB gain range with a step of 1dB, and the transmitter PGA（TXPGA） covers 16dB gain. The RXPGA consumes 18mA and the TXPGA consumes 7mA (I and Q path) under 3.3V supply. The bandwidth of the multi-stage PGA is higher than 20MHz. In addition, the DCOC (DC offset cancellation) circuit shows 10KHz of HPCF (high pass cutoff frequency) and the DCOC settling time is less than 0.45µs.     

DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation

To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations. Seok-Bae Park received the B.S. and M.S. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Ohio State University, Columbus, Ohio. He is currently with Firstpass Technologies, Inc., Dublin, Ohio as a Senior RF and Mixed-Signal Design Engineer. His current interests include low voltage/low power CMOS RF/analog/mixed-signal integrated circuits and systems for wireless communications. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the far east. He is Professor and The Founding Director of the Analog VLSI Lab, The Ohio State University. He advised the work of 40 PhD students and of 85 MS students. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has coedited and coauthored several books including a text on Analog VLSI Signal and Information Processing, McGraw Hill. His last book (2004) is entitled CMOS PLLs and VCOs for 4G Wireless, Springer. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Firstpass Technologies Inc., a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal’s Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada. He is a Fellow of IEEE.     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

一种应用于直接变频WLAN接收机带数字辅助直流失调消除功能的可变增益放大器

本文提出了一种包含数字辅助直流失调消除(DCOC)功能,应用于直接变频无线局域网接收机的可变增益放大器(PGA)电路。该PGA采用0.13微米标准CMOS工艺实现,芯片面积0.39平方毫米,在1.2伏电源电压下的功耗为6.5毫瓦。通过采用单环路单数模转换器(DAC)混合信号直流失调消除结构,直流失调消除的最小建立时间减小至1.6微秒,同时可变增益放大器的增益能够在-8分贝到54分贝间以2分贝的步长变化。该直流失调消除环路采用了一种分段式数模转换器以在不牺牲精度的前提下降低设计复杂度,并采用了特定的数字控制算法使得环路的直流失调消除响应时间能够在快慢两种模式间动态切换,以使可变增益放大器符合无线局域网应用的要求。     

一种带新型直流失调补偿电路的模拟数字控制可配置的自动增益控制器

本文提出一种可用于零中频接收机的模拟/数字控制可配置的自动增益控制环路的设计,应用一种新型的直流失调消除电路。这种自动增益控制环路可配置于模拟或者数字控制,以便与不同的基带芯片兼容。本文更进一步提出了一种新型的直流失调消除电路,这种直流失调消除电路实现了低于10KHz的下限截止频率（HPCF,high pass cutoff frequency）。自动增益控制环路电路采用0.18um CMOS工艺。当配置于模拟控制模式下,这种自动增益控制环路的增益动态范围为70dB,3dB带宽大于60M。当配置于数字控制模式下,通过5比特的数字控制码控制,这种自动增益控制环路的增益动态范围为64dB,步进精度2dB,步进误差小于0.3dB。当输入引入40mV直流失调,电路输出直流失调电压小于1.5mV。电路整体功耗小于3.5mA,面积800um*300um。     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A low-distortion CMOS IF VGA with linear-in-dB control and temperature compensation

A CMOS intermediate-frequency (IF) variable-gain amplifier (VGA) is presented in this paper. A transconductance linearization scheme is proposed for the VGA core based on a signal-subtracting structure to achieve low distortion. Temperature-independent decibel-linear gain control characteristic is achieved by an exponential voltage generator based on transfer characteristics of differential pair. The whole VGA, including a highly-linear output stage, is fabricated in 0.25 μm CMOS technology. Measurements show that the VGA provides a total gain control range of 43 dB with less than 1.2 dB error over 0–80°C, and a constant 3-dB bandwidth of 100 MHz. The third-order intermodulation (IM3) distortion at differential output of 2 V_PP is better than −55 dB. The VGA dissipates 22.6 mA averagely from 3.3 V supply, and occupies approximately 0.53 mm².     

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described.Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications.The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing.The calibra...     

一种带有直流失调和载波泄漏矫正系统的直接变频WLAN收发机基带电路

本文介绍了一种基于IEEE 802.11a/b/g标准的双频段直接变频WLAN收发机基带电路,并引入了一些用于消除接收机直流失调和发射机载波泄漏的关键技术,从而使得该直接变频结构满足WLAN的性能指标。在接收机基带中,可变增益放大器提供62dB的增益范围且步长为2dB;直流失调矫正电路用来消除由版图不匹配和自混频造成的误差。该矫正环路有着不随增益调节而变化的高通极点和较快的稳定时间,后者通过在接收前导序列时设定1MHz的高通极点而在正常接收数据时设定30KHz的极点得以实现。发射机基带采用基于片上AD和DA的自动矫正系统来抑制载波泄漏,AD在矫正完成之后会自动关闭从而可以节省功耗。此电路采用0.35微米锗硅工艺并工作在2.85V电源电压下,接收基带放大器和直流失调消除电路共消耗17.52mA,而发射载波泄漏矫正环路共消耗8.3mA（矫正完成后为5.88mA）;其相应的芯片面积分别为0.68mm2和0.18mm2。     

10 Gb/s 带有直流漂移校正的dB线性、无电感宽带可变增益放大器

本文介绍了一款带有直流漂移校正的dB线性、无电感宽带可变增益放大器。该可变增益放大器包含一个可变增益模块,一个带有共模电压调整的直流漂移校正模块,以及一个带宽拓展模块。为了放大器带宽同时节约芯片面积,本设计中带宽拓展模块采用了一种无电感设计的有源反馈技术,通过该模块在高频增益过冲来补偿可变增益模块和直流漂移校正模块在高频处的增益下降,从而达到拓展带宽、提高增益的效果。该可变增益放大器采用0.13mm SiGe BiCMOS工艺。测试结果表明,该款放大器3 dB带宽达到7.5 GHz,可变增益范围为40 dB (-10 dB-30 dB)。在10 Gb/s伪随机测试码输入的情况下,测试输出信号峰峰抖动小于30 ps_pp,功耗为50 mW。由于无电感设计,该芯片的面积仅为0.53*0.27 mm₂。     

一种应用于DRM/DAB调谐器的低噪声及dB线性中频可变增益放大器设计

A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.     

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

A broadband CMOS intermediate frequency (IF) variable-gain amplifier (VGA) for DRM/DAB tuners is presented. The VGA comprises two cascaded stages: one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18/zm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is-3.9 dBm.     

基于斩波技术的CMOS运算放大器失调电压的消除设计

实现传感器系统的高分辨率,要求其内部运算放大器具有低失调电压和低噪声的性能,为此介绍了一种可减少运算放大器的失调电压和低频噪声的斩波技术,并基于该技术进行温度传感器中CMOS运算放大电路失调电压的消除设计,最后通过SPICE仿真分析来权衡电路各参数的设定。     

一种具有双模检测功能和高稳定性的唤醒接收机基带电路

This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system.A double-mode detection method,including amplitude detection and frequency detection,is proposed to reject interference and reduce false wake-ups.An improved closed-loop band-pass filter and a DC offset cancellation technique are also newly introduced to enhance the sensitivity robustness.The circuit is fabricated in TSMC 0.18μm 3.3 V CMOS technology with an area of 0.12 mm2.Measurement results show that the sensitivity is -54.5 dBm with only a±0.95 dBm variation from the 1.8 to 3.3 V power supply,and that the temperature variation of the sensitivity is±1.4 dBm from -50 to 100℃. The current consumption is 1.4 to 1.7μA under a 1.8 to 3.3 V power supply.     

具有温度补偿及dB线性增益控制的单级宽范围CMOS可变增益放大器

提出了一种新颖的宽范围CMOS可变增益放大器结构.利用可变跨导和新颖的可变输出电阻,基于单独可变增益级的放大器可提供80dB的宽范围调节.同时控制电路的设计完成了温度补偿及dB线性增益特性,实现在整个温度及增益调节范围内绝对增益误差小于±1.5dB.基于0.25μm CMOS工艺验证表明,放大器可提供64.5dB的增益变化范围,其中dB线性范围为55.6dB.输入1dB压缩点为-17.5到11.5dBm,3dB带宽为65MHz到860MHz,2.5V电源供电下功耗为16.5mW.     

具有温度补偿及dB线性增益控制的单级宽范围CMOS可变增益放大器

提出了一种新颖的宽范围CMOS可变增益放大器结构.利用可变跨导和新颖的可变输出电阻,基于单独可变增益级的放大器可提供80dB的宽范围调节.同时控制电路的设计完成了温度补偿及dB线性增益特性,实现在整个温度及增益调节范围内绝对增益误差小于±1.5dB.基于0.25μm CMOS工艺验证表明,放大器可提供64.5dB的增益变化范围,其中dB线性范围为55.6dB.输入1dB压缩点为-17.5到11.5dBm,3dB带宽为65MHz到860MHz,2.5V电源供电下功耗为16.5mW.     

A low power 48-dB/stage linear-in-dB variable gain amplifier for direct-conversion receivers

In this paper, a low power Variable Gain Amplifier (VGA) circuit with an approximation to exponential gain characteristic is presented. It is achieved using current mirrors to generate appropriate current signals to bias the input stage of the VGA circuit working in triode region, and the output stage working in saturation region, respectively. The VGA circuit presented herein comes with a 549 μW maximum power consumption given a 1.8 V supply. Most important of all, it has a linear-in-dB 48-dB dynamic gain range per stage. The effect of the input trasconductance and the output resistance on the linearity of gain control is also discussed. This circuit is fabricated using a 0.18 μm standard CMOS process with a core area of 0.0045 mm².     

现代光通讯中的全集成CMOS限幅器及场强指示电路

针对各种光通信系统和射频通信系统中的应用,设计了一款限幅器及场强指示器(RSSI)电路,提出了一种新的直流漂移补偿方案,可使限幅器部分更加适合于全集成.对传统的RSSI电路作出了改进,大大提高了其工艺稳定性和温度稳定性.设计的限幅器具有72 dB的电压增益,可以对载波为1.5 MHz、带宽为1 MHz的中频信号进行放大;RSSI部分的动态范围为80 dBm,场强检测的误差小于±1 dB.     

CMOS可变增益放大器指数变化控制电路设计

文章设计了一种新颖的CMOS可变增益放大器增益指数变化控制电路。在理论分析一模拟乘法器的基础上,采用数学逼近的原理,提出实现了一种伪指数增益控制电路,得到很好的dB-线性特性。该电路工作电压3V,采用CSMC0．6μm工艺设计实现约30dB范围的增益控制。