一种应用于DRM/DAB调谐器的低噪声及dB线性中频可变增益放大器设计

A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.     

DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation

To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations. Seok-Bae Park received the B.S. and M.S. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Ohio State University, Columbus, Ohio. He is currently with Firstpass Technologies, Inc., Dublin, Ohio as a Senior RF and Mixed-Signal Design Engineer. His current interests include low voltage/low power CMOS RF/analog/mixed-signal integrated circuits and systems for wireless communications. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the far east. He is Professor and The Founding Director of the Analog VLSI Lab, The Ohio State University. He advised the work of 40 PhD students and of 85 MS students. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has coedited and coauthored several books including a text on Analog VLSI Signal and Information Processing, McGraw Hill. His last book (2004) is entitled CMOS PLLs and VCOs for 4G Wireless, Springer. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Firstpass Technologies Inc., a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal’s Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada. He is a Fellow of IEEE.     

一种具有双模检测功能和高稳定性的唤醒接收机基带电路

This paper proposes a baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness for use in the electronic toll collection system.A double-mode detection method,including amplitude detection and frequency detection,is proposed to reject interference and reduce false wake-ups.An improved closed-loop band-pass filter and a DC offset cancellation technique are also newly introduced to enhance the sensitivity robustness.The circuit is fabricated in TSMC 0.18μm 3.3 V CMOS technology with an area of 0.12 mm2.Measurement results show that the sensitivity is -54.5 dBm with only a±0.95 dBm variation from the 1.8 to 3.3 V power supply,and that the temperature variation of the sensitivity is±1.4 dBm from -50 to 100℃. The current consumption is 1.4 to 1.7μA under a 1.8 to 3.3 V power supply.     

应用于多模接收机的低功耗可编程增益放大器

针对多模接收机的应用,提出了引入一条闭环伪通路技术结构的可编程增益放大器,在保持一定的线性度及噪声性能的基础上,以较低的功耗实现较大的带宽.该电路增益步长为2 dB,增益变化范围1～39 dB.电路中内嵌了直流失调消除模块防止直流漂移引起的阻塞.芯片采用SMIC 0.13 μm 1P8M RF CMOS工艺实现.测试结...     

一种带新型直流失调补偿电路的模拟数字控制可配置的自动增益控制器

本文提出一种可用于零中频接收机的模拟/数字控制可配置的自动增益控制环路的设计,应用一种新型的直流失调消除电路。这种自动增益控制环路可配置于模拟或者数字控制,以便与不同的基带芯片兼容。本文更进一步提出了一种新型的直流失调消除电路,这种直流失调消除电路实现了低于10KHz的下限截止频率（HPCF,high pass cutoff frequency）。自动增益控制环路电路采用0.18um CMOS工艺。当配置于模拟控制模式下,这种自动增益控制环路的增益动态范围为70dB,3dB带宽大于60M。当配置于数字控制模式下,通过5比特的数字控制码控制,这种自动增益控制环路的增益动态范围为64dB,步进精度2dB,步进误差小于0.3dB。当输入引入40mV直流失调,电路输出直流失调电压小于1.5mV。电路整体功耗小于3.5mA,面积800um*300um。     

现代光通讯中的全集成CMOS限幅器及场强指示电路

针对各种光通信系统和射频通信系统中的应用,设计了一款限幅器及场强指示器(RSSI)电路,提出了一种新的直流漂移补偿方案,可使限幅器部分更加适合于全集成.对传统的RSSI电路作出了改进,大大提高了其工艺稳定性和温度稳定性.设计的限幅器具有72 dB的电压增益,可以对载波为1.5 MHz、带宽为1 MHz的中频信号进行放大;RSSI部分的动态范围为80 dBm,场强检测的误差小于±1 dB.     

一种高精度宽带可编程增益放大器设计

基于SMIC 180 nm混合信号CMOS工艺,1．8 V电源电压供电,设计了一种应用于射频前端芯片的高精度宽带全差分可编程增益放大器（PGA ）．该PGA采用四级级联结构,且带有直流失调校准电路和可驱动50Ω电阻负载的超级源随器．流片测试结果表明,该PGA性能良好,由六位数字控制字实现0～50 dB增益范围变化,1 dB步进,步长误差小于0．2 dB ,1 dB带宽大于75 M Hz ,3 dB带宽大于110 M Hz ,放大电路部分消耗9 mA电流,输出buffer电路部分消耗8 mA电流,芯片有效面积为518μm ×406μm ．     

一种用于射频接收机的模拟基带电路

设计了一种无线传感网射频接收机中的基带电路,包括滤波器和可变增益放大器(VGA)。滤波器采用5阶切比雪夫型有源RC结构,带宽可调,具有自动调谐功能,能适应制造工艺与环境条件的变化。VGA由2阶放大器与1阶缓冲器组成,每阶放大器拥有一个DCOC环路,用来抑制直流失调,减小增益瞬态变化的稳定时间。采用TSMC 130 nm CMOS工艺进行流片。测试结果表明,供电电压为1.3 V时,滤波器能够涵盖8种带宽。自动调谐模块的调谐范围为±20%,调谐精度为2%。接收机的IIP3为28 dBm,双边带噪声为3 dB。VGA的增益变化范围为-12~56 dB。当VGA的增益瞬态变化量为32 dB时,DCOC的稳定时间小于100 ns。     

一种dB线性数字控制可变增益放大器的设计

设计了一种dB线性增益的数字控制可变增益放大器。以二极管做负载的全差分输入共源极放大器为原型,通过同时同比例地改变输入输出晶体管尺寸比和偏置电流比来控制增益变化,使输入输出晶体管的电流密度保持一恒定值,提高了电路在低增益时的线性度。电路采用NEC 0.35μm CMOS标准工艺库进行设计。仿真结果表明,dB线性增益范围为-11.85dB到11.64dB,增益误差小于0.5dB。增益为-11.85dB时,其1-dB压缩点达到8.35dBm,-3dB增益带宽大于62MHz,并且随设定的增益值在62MHz和240MHz之间变化。     

一种适用于严重衰减串行链路的3.3 Gbit/s模拟均衡器

介绍了一种用于严重损耗串行链路的连续时间线性均衡器(CTLE)。为了解决传统均衡器存在的过均衡和欠均衡问题,提出了一种低频增益线性可调的改进结构,实现了对不同衰减信道的增益补偿。该结构主要包括均衡滤波模块和直流失调消除模块。均衡滤波模块采用均衡单元串联的结构,提高了对信号高频成分的补偿能力。直流失调消除模块用来消除芯片制造过程中因失配而产生的直流偏移。电路采用TSMC 0.18μm CMOS工艺设计,总面积为1.2 mm×0.65 mm。测试结果表明,当速率为3.3 Gbit/s的数据通过损耗为18.8 dB的信道时,均衡器工作正常。在1.8 V的供电电压下,芯片整体功耗为124.2 mW。     

两个重要改进提高了RFID读写器的性能

基于无源电子标签的RFID读写器系统通常采用所谓“零中频”接收方案,采用该方案会造成射频信号发射端和接收端之间的载波泄漏,其结果是一方面接收机前端容易饱和因而减少了系统通信距离;另一方面会带来所谓的“直流偏移”问题从而增加了系统误码率．本文提出了两个措施来解决或改善这一问题．首先,将载波抵消技术应用到2.45 GHz频段的RFID读写器中,采用微带电路进行载波泄漏抵消电路的设计,通过ADS软件仿真、制作并测试样机,文中给出了改进后环行器泄漏功率的抵消结果．其次,提出一种带有直流反馈环路的宽带高增益直流放大器,用于放大基带信号并自动补偿混频器带来的直流分量,输出波形无明显失真,从而降低了读写器读取电子标签数据的误码率．     

10 Gb/s 带有直流漂移校正的dB线性、无电感宽带可变增益放大器

本文介绍了一款带有直流漂移校正的dB线性、无电感宽带可变增益放大器。该可变增益放大器包含一个可变增益模块,一个带有共模电压调整的直流漂移校正模块,以及一个带宽拓展模块。为了放大器带宽同时节约芯片面积,本设计中带宽拓展模块采用了一种无电感设计的有源反馈技术,通过该模块在高频增益过冲来补偿可变增益模块和直流漂移校正模块在高频处的增益下降,从而达到拓展带宽、提高增益的效果。该可变增益放大器采用0.13mm SiGe BiCMOS工艺。测试结果表明,该款放大器3 dB带宽达到7.5 GHz,可变增益范围为40 dB (-10 dB-30 dB)。在10 Gb/s伪随机测试码输入的情况下,测试输出信号峰峰抖动小于30 ps_pp,功耗为50 mW。由于无电感设计,该芯片的面积仅为0.53*0.27 mm₂。     

一种应用于直接变频WLAN接收机带数字辅助直流失调消除功能的可变增益放大器

本文提出了一种包含数字辅助直流失调消除(DCOC)功能,应用于直接变频无线局域网接收机的可变增益放大器(PGA)电路。该PGA采用0.13微米标准CMOS工艺实现,芯片面积0.39平方毫米,在1.2伏电源电压下的功耗为6.5毫瓦。通过采用单环路单数模转换器(DAC)混合信号直流失调消除结构,直流失调消除的最小建立时间减小至1.6微秒,同时可变增益放大器的增益能够在-8分贝到54分贝间以2分贝的步长变化。该直流失调消除环路采用了一种分段式数模转换器以在不牺牲精度的前提下降低设计复杂度,并采用了特定的数字控制算法使得环路的直流失调消除响应时间能够在快慢两种模式间动态切换,以使可变增益放大器符合无线局域网应用的要求。     

An integrated front-end vertical hall magnetic sensor fabricated in 0.18 μm low-voltage CMOS technology

An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measurement. To improve the magnetic sensitivity and to obtain low offset, a fully symmetric vertical Hall device (FSVHD) has been optimized with a minimum size design. A new four-phase spinning current modulation associated with a correlated double sampling (CDS) demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage. The vertical Hall sensor chip has been manufactured in a 0.18 μm low-voltage CMOS technology and it occupies an area of 1.54 mm². The experimental results show in the magnetic field range from –200 to 200 mT, the entire vertical Hall sensor performs with the linearity of 99.9% and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60 μT. Meanwhile, it consumes 4.5 mW at a 3.3 V supply voltage. The proposed vertical Hall sensor is very suitable for the low-cost system-on-chip (SOC) implementation of 2D or 3D magnetic microsystems.