A 170 MHz RF front-end for ERMES pager applications

A 170 MHz RF front-end for ERMES pager applications has been implemented in a 1.2 μm BiCMOS technology. The chip comprises a low noise amplifier with AGC, a double balanced mixer, a varactor tuned LC local oscillator, and an IF strip containing an AGC amplifier and a double balanced mixer with integrated active output filter. The LNA has a measured gain of 22.3 dB at 170 MHz with a usable AGC range of approximately 20 dB while the conversion transconductance of the mixer is 130 μS. This front-end is suitable for direct conversion and superheterodyne pager receivers, and its noise figure is 6.2 dB. Low power operation has been achieved with the front-end drawing 230 μA at 3 V, which is compatible with the intended application in wrist-watch style pagers     

A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner

A high dynamic range RF variable gain amplifier (RFVGA) suitable for mobile digital television (DTV) tuners is presented. Variable gain is achieved using a capacitive attenuator and current-steering transconductance (G_m) stages, which provide high linearity with relatively low power consumption. A novel broadband input impedance matching scheme based on resistive shunt-feedback is proposed. This scheme allows the RFVGA to achieve a low noise figure. A gain control technique suitable for CMOS current-steering variable gain amplifiers is described; it features 1 dB per step resolution, independent of process and temperature variations. The chip is fabricated in six-metal 0.18mum CMOS technology and consumes 12.2mA current from 1.8V supply. The RFVGA achieves 16dB maximum gain, 33dB gain control range, a 4.3dB noise figure, and an IIP3 higher than 25dBm     

基于0.18μm CMOS工艺2.5Gb/s宽动态范围光接收机前端放大电路设计

基于0.18μm CMOS工艺设计了适用于2.5Gb/s传输速率的宽动态范围光接收机前端放大电路（包括前置放大器和限幅放大器）.前置放大器采用了RGC输入级的跨阻放大器,并且应用了消直流电路和自动增益控制电路扩展输入动态范围.限幅放大器采用了按比例缩小尺寸、并联峰化和带有有源负反馈的Cherry-Hooper放大器等方法扩展带宽.仿真结果表明：前端放大电路的中频增益为116dBΩ,-3dB带宽为2.13GHz,输入信号动态范围为40dB（0.01～1mA）.     

A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band lIP3 of-5.1 dBm. The receiver occupies 2.3 mm2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.     

A tri-mode Compass/GPS/Galileo RF receiver with all-digital automatic gain control loop

A tri-mode RF receiver with all digital automatic gain control (AGC) loop and non-uniform 2-bit analog-to-digital converter (ADC) is designed for the bands of GPS-L1, Galileo-E1 and Compass B1 in 0.18 μm CMOS process. The RF front-end, analog baseband and frequency synthesizer with voltage controlled oscillator (VCO) have been integrated, and there are only few off-chip components including bypass capacitances, matching network and TCXO. For anti-jamming consideration, an all digital AGC loop with relevant variable gain amplifier (VGA) and non-uniform ADC is implemented to suppress interference and avoid saturation of signal chain. While drawing 35 mA current, this receiver achieves a total noise figure of 4 dB and a maximum gain of 105 dB, with a die area of 2.4 × 2.4 mm².     

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as f_T-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 2³¹–1 with a bit-error rate (BER) of 10⁻¹² at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mV_pp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.     

A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10^-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.     

Jitter considerations in the design of a 10-Gb/s automatic gain control amplifier

The effects of noise on random jitter in multistage broad-band amplifiers are analyzed. Limiting amplifiers are compared to automatic gain control (AGC) amplifiers with different gain profiles. Results are presented for a 10-Gb/s AGC amplifier implemented in an SiGe process with f_T of 45 GHz. Active peaking techniques were used to achieve a maximum gain of 48 dB with 7.8 GHz of bandwidth. The amplifier demonstrates low jitter and less than 0.5 dB of peak-to-peak output amplitude variation over a 50-dB input amplitude range. It consumes 30 mW of power from a 3.3-V supply. The amplifier core occupies 0.1 mm² and requires no external components     

Wideband and high-gain negative-feedback AGC amplifier for high-speed lightwave digital transmission systems

A negative-feedback AGC amplifier based on a new circuit configuration concept is proposed and monolithically integrated. The amplifier exhibits characteristics 2.5 times superior to those of the conventional AGC amplifier: 410 MHz bandwidth, 16 dB maximum gain and 18 dB gain dynamic range.     

Wideband monolithic AGC amplifier for 400 Mbit/s optical repeaters using an advanced Si-bipolar IC technology, SICOS

A wideband AGC amplifier is monolithically integrated using an advanced Si-bipolar IC technology, SICOS. The fabricated IC exhibits an 8·4 dB maximum gain, 17 dB variable gain and 1·1 GHz bandwidth. It is shown that the SICOS technology is feasible for developing an equalising amplifier with a 37 dB gain and 700 MHz bandwidth for 400 Mbit/s optical repeaters.     

A GaAs upconverter MMIC with an automatic gain control amplifierfor 1.9 GHz PHS

A newly developed GaAs upconverter MMIC with an automatic gain control (AGC) amplifier is presented. The design objectives, considerations, problems, and their solutions are described. The circuit is designed for a 1.9 GHz radio-frequency transceiver for the Japanese Personal Handyphone System applications. The features of the upconverter are: (1) on-chip 50 Ω impedance matching for all AC input and output signals; (2) a doubly balanced Gilbert cell and a two-stage AGC amplifier with matching circuits that provide 23.0 dB conversion gain, -39 dBc LO suppression, -23 dBc image suppression, and 30 dB gain control; (3) an adjacent channel power of -70 dBc, and (4) a die size of only 2.87 mm² (2.52 mm×1.14 mm)     

CMOS宽带可编程增益低噪声放大器

给出了一种可应用于中国移动多媒体广播(CMMB)调谐器的宽带(470~860 MHz)可编程增益低噪声放大器。该电路在UMC 0.18μm RF CMOS工艺下实现,芯片面积为0.37 mm2(不包括ESD pad)。芯片测试结果表明,在1.8 V的电源电压下功耗为30.2 mW,该电路可实现-6.8~32.4 dB的增益动态变化范围,0.5 dB步长,最高增益下单端信号噪声系数小于3.8 dB。     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

A high-performance low-power CMOS AGC for GPS application

A wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier (VGA), a comparator and a charge pump, and the dB-linear gain is controlled by the charge pump. The AGC was implemented in a 0.18 μm CMOS technology. The dynamic range of the VGA is more than 55 dB, the bandwidth is 30 MHz, and the gain error is lower than ±1.5 dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8 V power supply.The AGC power consumption is less than 5 mW, and the area of the AGC is 700 × 450 μm~2.     

A channel-number insensitive erbium-doped fiber amplifier withautomatic gain and power regulation function

The design scheme for an erbium-doped fiber amplifier (EDFA) with automatic channel-by-channel gain and power regulation function is discussed with much emphasis on the pump power control scheme and the requirement for feedback circuitry. Based on both wavelength and time-resolved simulation technique, an amplifier repeater employing novel high-speed automatic gain control (AGC) and automatic level control (ALC) functions is designed and implemented. The AGC and ALC scheme can suppress the transient power fluctuation of a surviving channel caused by adding or dropping all other channels less than 0.45 dB and keep output power constant over 9-dB input power range     

应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器

这篇文章呈现了一个应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器,使用了改进的带负电容抵消技术Cherry-hooper放大器作为增益单元,采用了新颖的电路技术来实现增益调节,该技术在宽带PGA的设计中具有普适性,并且可以大大简化宽带PGA的设计。PGA通过两级增益单元和一级输出BUFFER的级联获得了最大增益30dB和远宽于3GHz的带宽。该PGA集成进整个60GHz无线收发机里面并且用TSMC65nm的CMOS工艺获得实现。整个接收机前端的测试结果表明接收机前端获得了18dB的可变增益范围和>3GHz的带宽,这证明提出的PGA本身获得了18dB的可变增益范围并且带宽是远大于3GHz的。该PGA电源电压为1.2V,功耗为10.7mW,核心版图面积仅仅为0.025mm^2。     

Bipolar monolithic amplifiers for a gigabit optical repeater

Main amplifier, AGC amplifier, and preamplifier ICs have been designed and fabricated using an advanced silicon bipolar process to provide the required characteristics of repeater circuits for a gigabit optical fiber transmission system. The bipolar technology used involved a separation width of 0.3 /spl mu/m between the emitter and the base electrode. New circuit techniques were also used. The differential type main amplifier has a peaking function which can be varied widely by means of DC voltage supplied at the outside IC terminal. A bandwidth which can be varied to about three times the value for a nonpeaking amplifier is easily obtained. The gain and maximum 3-dB down bandwidth were 4 dB and 4 GHz, respectively. The main feature of the AGC amplifier is that the diodes are connected to the emitters of the differential transistor pair to improve the linearity. The maximum gain and 3-dB down bandwidth were 15 dB and 1.4 GHz, respectively, and a dynamic range of 25 dB was obtained. The preamplifier has a shunt-series feedback configuration. Furthermore, a gain and 3-dB down bandwidth of 22 dB and 2 GHz, respectively, were achieved with an optimum circuit design. The noise figure obtained was 3.5 dB.     

应用于无线传感器网络低噪声放大器的设计

本文给出一种应用于无线传感器网络射频前端低噪声放大器的设计,采用SMIC0．18μmCMOS工艺模型。在CadenceSpectre仿真环境下的仿真结果表明：该低噪声放大器满足射频前端的系统要求,在2．45GHz的中心频率下增益可调,高增益时,噪声系数为2．9dB,输入P1dB压缩点为-19．8dBm,增益为20．5dB;中增益时,噪声系数为3．6dB,输入P1dB压缩点为-15．8dBm,增益为12．5dB;低增益时,噪声系数为6．0dB,输入P1dB压缩点为-16．4dB,增益为2．2dB。电路的输入输出匹配良好,在电源电压1．8V条件下,工作电流约为6mA。     

A fast configurable AGC for front-end of digital hearing aids

This paper presents a fast configurable automatic gain control (AGC) with strong focus on fast acting control and low power consumption. This AGC includes two paths, main amplification path and gain adjusting path. Using the gain adjusting path through an extra amplifier provides a way for tracking and comparing the input signal with four adjusted thresholds to be judged for selecting the appropriate gain value for main amplification path. This mechanism of gain control is done by reorganization of input level and changing the resistance of feedback in main amplification path to generate smooth variation gain, without any interruption or delay in signal flow through the variable gain amplifier. Moreover, in order to protect the user from intense transients in variations of the input signal level, output level of variable gain amplifier is directly monitored using optimum threshold to reduce the overall gain using feedback control mechanism. The minimum power is consumed by gain adjusting path has almost no considerable on power consumption, it greatly improves hearing quality. Meanwhile, using a large size PMOS differential pair at the input improved the noise performance. Proposed AGC designed and simulated in TSMC 130-nm CMOS process. The post layout simulation results the maximal SNR is 84.6 dB in 100 Hz–19.6 kHz band-width and the total consumption power of this AGC is 78 μW at 1 V supply voltage. In addition, its gain is varied smoothly between 20 to 57 dB. Achieved results demonstrate that designed AGC meet the requirement of analog front end of hearing aids.

     

433MHz ASK接收机射频前端电路设计

设计了一款应用在433MHz ASK接收机中的射频前端电路。在考虑了封装以及ESD保护电路的寄生效应的同时,从噪声、匹配、增益和线性度等方面详细讨论了低噪声放大器和下混频器的电路设计。采用0.18μm CMOS工艺,在1.8V的电源电压下射频前端电路消耗电流10.09 mA。主要的测试结果如下:低噪声放大器的噪声系数、增益、输入P1dB压缩点分别为1.35 dB、17.43 dB、-8.90dBm;下混频器的噪声系数、电压增益、输入P1dB压缩点分别为7.57dB、10.35dB、-4.83dBm。