A low power dual-band multi-mode RF front-end for GNSS applications

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS,Bei-Dou,Galileo and Glonass systems is presented.It consists of a reconfigurable low noise amplifier(LNA),a broadband active balun,a high linearity mixer and a bandgap reference(BGR) circuit.The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail.By using two different LC networks at the input port and the switched cap...     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

一种5~6 GHz宽带全集成CMOS低噪声放大器

采用55 nm标准CMOS工艺,设计并流片实现了一种应用于Wi-Fi 6(5 GHz)频段的宽带全集成CMOS低噪声放大器(LNA)芯片,包括源极退化共源共栅放大器、负载Balun及增益切换单元。在该设计中,所有电感均为片上实现;采用Balun负载,实现信号的单端转差分输出;具备高低增益模式,以满足输入信号动态范围要求。测试结果表明,在高增益模式下该放大器的最大电压增益为20.2 dB,最小噪声系数为2.2 dB;在低增益模式下该放大器的最大电压增益为15 dB,最大输入1 dB压缩点为-3.2 dBm。芯片核心面积为0.28 mm²,静态功耗为10.2 mW。     

A 20-GHz low-noise amplifier with active balun in a 0.25-/spl mu/m SiGe BICMOS technology

A 20-GHz low-noise amplifier (LNA) with an active balun fabricated in a 0.25-/spl mu/m SiGe BICMOS (f/sub t/=47 GHz) technology was presented by the authors in 2004. The LNA achieves close to 7 dB of gain and a noise figure of 4.9 dB with all ports simultaneously matched to 50 /spl Omega/ with better than -16 dB of return loss. The amplifier is highly linear with an IP/sub 1dB/ of 0 dBm and IIP/sub 3/ of 9 dBm, while consuming 14 mA of quiescent current from a 3.3-V rail, with temperature-compensated biasing. To the authors' knowledge, the LNA delivers the lowest reported noise figure and highest linearity for a silicon implementation of a combined active balun and LNA at 20 GHz, and is the first implementation of an active balun with an LC degenerated emitter-coupled pair. Here we expand on that work, with an analysis of the balun operation and noise optimization of the design.     

Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier(LNA) and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm~2 die size.     

A switch‐controlled multimode narrowband receiver RF front‐end

This work illustrates a flexible and convenient method to build a multimode narrowband receiver RF front‐end by means of controlled switches, switched capacitors, and switched inductors. The front‐end comprises a dual‐gain‐mode narrowband low‐noise amplifier (LNA) and a dual‐linearity‐mode mixer. A four‐mode receiver RF front‐end constructed with the dual‐gain‐mode LNA and the dual‐linearity‐mode mixer operating in frequency band range from 1800 to 2050 MHz was demonstrated with an IBM 90‐nm CMOS process. The front‐end achieves a 1/1.6 dB noise figure, 30/20 dB power gain, and 16/?10 dBm third‐order input intercept point while draws a 5.9/3.6 mA current from a 1.8‐V supply voltage at the low noise mode and high linearity mode, respectively. The proposed technique can be employed to build an intelligent mobile system.     

2.4GHz带片上非平衡变压器射频前端的设计与优化

本文介绍了一种工作在2.4GHz频段的低功耗、低噪声、高线性射频接收机前端电路,该接收前端电路使用新型的带三种增益模式的LNA,并提出一种新的片上非平衡变压器优化技术。前端电路采用了直接变频结构,使用片上非平衡变压器实现低噪声放大器与下变频混频器之间的单端-差分转换,优化设计以提高前端电路的噪声性能。本文使用锗硅0.35um BiCMOS工艺,所采用的技术同样适用于CMOS工艺。前端电路总的最大转换增益为36dB;在高增益模式下的双边带噪声系数为3.8dB;低增益模式下,输入三阶交调点位12.5dBm。为了获得最大的输入动态范围,低噪声放大器采用三种可调增益模式,低增益模式使用by-pass结构,大大提高了大信号输入下接收前端的线性度。下变频混频器在输出端使用可调R-C tank,滤除带外高频杂波。混频器输出使用射极跟随器作为输出极驱动片外50ohm负载。该接收前端在2.85-V电源供电下,功耗为33mW,芯片面积为0.66mm2。     

Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

A post-linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive-channel metal oxide semiconductor field-effect transistor for sinking the third-order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18-/spl mu/m technology. The LNA achieved +13.3-dBm IIP3 with 12.8-dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8-V supply.     

一种采用后失真技术的高线性巴伦低噪声放大器

宽带低噪声放大器能同时接收多路信号,这些信号会相互成为干扰源,因此要求宽带低噪声放大器同时具有较高的IIP2和IIP3,抑制这些干扰。在传统共栅共源巴伦低噪声放大器的基础上,对决定噪声和线性度的共源级采用了后失真技术。通过一个PMOS辅助管,对共源级输出信号的二次和三次非线性项都进行了抑制,使得整个放大器的线性度得到较大的提升。在0.2~4.35 GHz的范围内,该放大器的IIP2大于23 dBm,IIP3大于5 dBm。另外,共源放大管的衬底电阻对放大器有较大的噪声贡献,通过串接一个衬底大电阻,将其噪声贡献由10%降低到了1%左右。     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz60 MHz low noise amplifier (LNA) designed in a 0.35 m SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure (NF) of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point (IP1dB) of ?11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.     

A novel high dynamic range differential LNA using quartet topology

In some applications such as short-range radars, a large target can desensitize the receiver. A high dynamic range low-noise amplifier (LNA), as a key component of a transmitter/receiver module, can improve the entire system performance. This study presents a high dynamic range differential LNA that uses a differential quartet topology for the first time. The LNA shows more linearity than the conventional differential common source LNAs. For a typical 0.18 µm CMOS technology, it achieves a power gain of about 5.5 dB at 24 GHz, a low noise figure (NF) of 3.5 dB, very good linearity performance, an input-referred third-order intercept point (IIP3) of +?6.3 dBm, and an input-referred 1 dB compression point (P1dB) of ??4.5 dBm.     

Noise current feedforward for noise cancellation in the wideband transformer shunt feedback low noise amplifier

A noise current feedforward (NCF) technique for noise cancellation in the wideband transformer shunt feedback (TSF) low noise amplifier (LNA) is proposed. The NCF can detect and cancel the thermal noise of the TSF network. It is also suitable to cancel those noise contributed by the passive unilateral shunt feedback networks in common current mode LNAs. Implemented in SMIC 0.18 μm CMOS process and operated in the typical radio astronomy frequency range from 0.6 GHz to 1.6 GHz, the TSF LNA that employs the NCF shows approximately 0.2–0.5 dB lower noise figure than the overwhelming resistive shunt feedback LNA that exploits a conventional noise voltage feedforward technique when consuming the same power.     

Inductor-less PVT robust gain switching balun LNA for multistandard applications

An inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor C_c is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in g_m is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.     

A 0.18μm CMOS gain-switched LNA and mixer with large dynamic range

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier （LNA） and a passive mixer with no external balun for near-zero-IF （Intermediate Frequency）/RF （Radio Frequency） applications are described. The LNA, fabricated in the 0.18μm 1P6M CMOS technology, adopts a gain-switched technique to increase the linearity and enlarge the dynamic range. The mixer is an IQ-based passive topology. Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω. Combining LNA and mixer, the front-end measured performances in high gain state are： -15dB of Sll, 18.5dB of voltage gain, 4.6dB of noise figure, 15dBm of IIP3, 85dBm to -10dBm dynamic range. The full circuit drains 6mA from a 1.8V supply.     

A 0.18μm CMOS GAIN-SWITCHED LNA AND MIXER WITH LARGE DYNAMIC RANGE

A 2.4GHz 0.18μm CMOS gain-switched single-end Low Noise Amplifier(LNA) and a passive mixer with no external balun for near-zero-IF(Intermediate Frequency)/RF(Radio Frequency) applications are described.The LNA,fabricated in the 0.18μm 1P6M CMOS technology,adopts a gain-switched technique to increase the linearity and enlarge the dynamic range.The mixer is an IQ-based passive topology.Measurements of the CMOS chip are performed on the FR-4 PCB and the input is matched to 50Ω.Combining LNA and mixer,the front...     

Low-power and low NF V-band down-converter in 0.13 μm CMOS

A V-band down-converter integrating a LNA and mixer in 0.13 mm CMOS technology is presented. The LNA has a current re-use topology for low power consumption. The transistor size of the LNA is optimised by the substrate noise for the low noise figure (NF) and f_max for high gain performance. The new resistive mixer for low LO power operation is proposed. The NF of the down-converter is 4.7 dB. The conversion gain and input P_1dB are 0.67 dB and 212.5 dBm, respectively. The proposed circuit, consuming only 11.6 mW, shows the lowest NF and highest linearity among V-band down-converters.     

一种用于UHF RFID阅读器的无电感巴伦LNA设计

设计了一款用于UHF RFID射频前端接收机的高线性度LNA。该低噪声放大器采用噪声消除技术,具有单端输入差分输出的功能,能够同时实现输出平衡,噪声消除和非线性失真抵消,具有高的线性度。该电路采用TSMC0.18μm工艺设计,芯片面积只有0.02 mm2。电源电压为1.8 V,总电流为8 mA,后仿真结果增益为19.2 dB,噪声因子为2.5 dB,输入1 dB压缩点为-5.2 dBm。     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.