一种高线性低功耗基带Gm-C滤波器

介绍了一种应用于无线局域网(WLAN)收发机系统的跨导-电容(Gm-C)低通滤波器,该电路可工作于低电压,并且具有高线性度.该射频发射器中的滤波器采用截止频率为9.9 MHz的3阶切比雪夫低通滤波器,在30 MHz频率处的阻带衰减达到30.5 dB.由于采用跨导线性环技术,滤波器工作于1.2V电源电压时,IIP3可达13.5 dBm.电路采用0.13 μm CMOS工艺实现,滤波器芯片尺寸为0.52 mm×0.17 mm,消耗电流3.76 mA.     

A New CMOS Programmable Balanced Output Transconductor and Application to a Mixed Mode Universal Filter Suitable for VLSI

A new CMOS programmable balanced output transconductor (BOTA) is introduced. The BOTA is a useful block for continuous-time analog signal processing. A new CMOS realization based on MOS transistors operating in the saturation region is given. Application of the BOTA in realizing a mixed mode universal filter using six BOTAs and two grounded capacitors is also introduced. The filter's gain can be adjusted simply by varying the amplitude of a transconductance through its control voltage without affecting ₀ and Q of the filter. Also, the Q of the filter can be adjusted by a single transconductor independent of ₀. PSpice simulation results for the BOTA circuit and for the universal filter are also given.     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.     

A reconfigurable OTA-C baseband filter with wide digital tuning for GNSS receivers

The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μm RFCMOS process is proposed.The filter can be configured as a complex band pass filter or two real low pass filters.An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations.An extended tuning range(above 8:1) is obtained by using widely continuously tunable transconductors based on digital techniques.In the complex band pas...     

All-Optical Demultiplexing of WLAN and Cellular CDMA Radio Signals

Subcarrier multiplexed transmission of multimedia radio signals over fiber is often done to deliver broadband services cost effectively. These signals need to be demultiplexed, preferably in the optical domain, to avoid loss and noise due to optical-to-electrical conversion. However, it is challenging to optically isolate signals at subgigahertz range due to the need for very narrow optical bandpass filters with high selectivity and low insertion loss and distortion. We developed such a novel subpicometer all-optical bandpass filter by creating a resonance cavity using two closely matched fiber Bragg gratings. This filter has a bandwidth of 120 MHz at -3 dB, 360 MHz at -10 dB, and 1.5 GHz at -20 dB. Experimental results show that this filter optically separates two RF signals spaced as close as 50 MHz without significant distortion. This paper analytically and experimentally investigates the scenario when this filter was used with 2.4-GHz (wireless local area network) and 900-MHz (cellular wireless) radio signals. The bit-error rate of the underlying baseband data is related to the linearity and isolation of the filter.     

Noise-Shaping Gain-Filtering Techniques for Integrated Receivers

In this paper, a new technique for realizing area-efficient, low-noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the passband of the filter. This is illustrated by implementing a programmable noise-shaped post-mixer gain-filtering circuit for a CMOS Mobile-TV tuner. The proposed circuits relax the noise-linearity tradeoff in the receiver chain by providing blocker rejection following the mixer outputs. The filter provides an in-band input referred noise density as low as 7.5 nV/sqrt(Hz). The measured out-of-band IIP3 values are 30 dBV and 31.5 dBV for the 3.8-MHz (DVB-H) and 750-kHz (ISDB-T) modes, respectively. Total current consumption is 5.5 mA from a 1.2-V supply. The gain of the block is programmable to be 0 dB, 8 dB, 14 dB, or 20 dB. The design occupies a die area of 0.28 mm² in a 65-nm CMOS process covering a frequency band of 700 kHz to 5.2 MHz as a universal mobile-TV integrated baseband gain-filtering solution.     

A current-mode continuous-time filter for software defined radio solutions

A 3rd-order continuous-time current-mode filter in 65 nm CMOS technology is presented. The filter has a switchable cut-off frequency between 1.1 and 4.4 MHz and is designed for software defined radio on chip (SDR) solutions. An innovative extension to structures in literature is proposed, that allows saving chip area at low cut-off frequencies. Furthermore a mathematical estimation is presented to show the usability of the structure. The realized chip has an active area of 350 μm × 220 μm and consumes 12.3 mW at 1.2 V. The dynamic range for a bandwidth of 1.1 MHz is 77.2 dB, the in-band output current noise is \(31.16\,\hbox{pA}/\sqrt{\hbox{Hz}}\) and the IIP3 is 1.8 mA_p.     

A technique to compensate an influence of mobility degradation by combining a source coupled pair with a transconductor

A transconductor is a basic building for integrated analogue circuits. High linearity of the transfer characteristic is necessary to a transconductor. However, along with miniaturisation of a device, linearity of the transconductor has deteriorated because of the mobility degradation from an effect of a vertical electric field. This paper proposes a new technique to reduce the influence of mobility degradation and to improve linearity of a transconductor. In order to improve the linearity, a source-coupled pair is combined with the transconductor. It is confirmed that the proposed technique reduces the transconductance error by about 1/5. For a sinusoidal input voltage of 1 V_p-p and 1 MHz, the total harmonic distortion is 3% or less.     

一种带有精准调谐结构的有源RC低通滤波器的设计

提出了一种带有精准调谐结构的有源RC低通滤波器的设计方案,其截止频率为5MHz,并在0.18μm标准CMOS工艺线上流片得到验证.调谐精度达到(-1.24%,+2.16%),测试中得到验证.调谐系统所占芯片面积仅为主滤波器面积的1/4.调谐系统完成调谐功能后会自动关闭,降低了功耗以及对主滤波器的串扰.以50Ω作为源阻抗,滤波器带内3阶交调量(IIP3)好于16.1dBm.滤波器输入参考噪声为36μVrms.滤波器群延迟时间波动测试结果为24ns.滤波器功耗为3.6mW.带有这种调谐结构的滤波器容易被实现,可以用于很多无线低中频应用中,例如全球定位系统、全球通和码分多址等芯片系统中.     

一种宽带多模数字抽取滤波器

提出了一种应用于连续时间Σ-Δ ADC的多模数字抽取滤波器。通过采用不同类型滤波器级联结构,合理分配不同级间下采样因子,有效降低了电路复杂度、面积和功耗。通过级间滤波器相互配合,实现了该滤波器的多带宽、多模式功能。基于65 nm CMOS工艺进行后端设计,仿真结果表明,该多模抽取滤波器的工作带宽为20~50 MHz,当工作带宽为20 MHz和50 MHz时,有效位数分别为10.64位和10.48位。     

A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques

A fully differential wideband sixth-order switched-capacitor bandpass filter is designed for channel selection in cable TV applications. A modified double-sampling pseudo-two-path technique is proposed to achieve a second-order wideband bandpass filter with a single opamp. Implemented in a standard double-poly four-metal 0.35-/spl mu/m CMOS process and operated at 176-MHz sampling frequency, the filter achieves a measured center frequency of 44 MHz with a bandwidth of 6.28 MHz and a dynamic range of 58.3 dB at 3% IM3. The filter consumes 92.5mW at a single 3.0-V supply and occupies a chip area of 0.52 mm /sup 2/.     

A monolithic CMOS 2368/spl plusmn/30 MHz transformer based Q-enhanced series-C coupled resonator bandpass filter

A three-pole 0.1 dB ripple Chebyshev series-C coupled resonator bandpass filter with transformer-based Q-enhancement is presented. This Q-enhancement technique compensates resonator loss and produces a flat passband response with low insertion loss. The compensation scheme uses frequency-dependent negative resistance to compensate frequency-dependent inductor losses, avoiding passband distortion, which is a problem with cross-coupled negative resistance circuits. Fabricated in 0.18 /spl mu/m CMOS, the measured filter center frequency is 2368 MHz with a 60 MHz (3 dB) bandwidth, including probe pad and connecting trace parasitic losses. The filter draws 5.84 mA at 1.5 V, and the die area is 1.5 mm/spl times/1.5 mm.     

High multiplication factor capacitor multiplier for an on-chip PLL loop filter

A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) loop filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 μA. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 μm CMOS technology to employ the proposed capacitor multiplier.     

一种高线性Gm-C复数滤波器的设计

针对低电源电压Gm-C复数滤波器线性度不足的问题,提出了一种使用大信号线性化技术的一阶复数带通滤波器。所提出的复数滤波器使用了不平衡差分对和自适应偏置电路两种线性化技术,通过扩展跨导相对恒定的输入电压范围提高滤波器的线性度。滤波器采用UMC 110 nm CMOS工艺设计,中心频率和带宽分别为2 MHz和1 MHz。Cadence仿真结果显示,在1.2 V电源电压下,滤波器功耗为229μW,镜像抑制比(IIR)为18 dB,线性度(输入三阶交调点IIP3)为9.53 dBm,总谐波失真(THD)为-55.7 dB。该复数滤波器电路结构简单、功耗较低,以期能广泛应用于低电源电压的接收机设计。     

A new CMOS channel select filter for dual mode bluetooth/WLAN direct-conversion receiver

Design of a CMOS 4th-order channel select filter for integrated dual mode Bluetooth/WLAN direct-conversion receiver is presented. The bandwidth of the filter can be programmed from 200 kHz to 8 MHz to accommodate both standards. The proposed filter provides low power, and small area design solution. Post-layout simulation results show that the filter satisfies the selectivity and dynamic range requirements of both applications while consuming total standby power of 1.88 mW.     

可切换带宽的可调频率带通滤波器设计

提出了一种可切换固定带宽的可调频率带通滤波器新结构,且实现了在带宽切换前后都能保持固定带宽的特性。基于谐振线间的耦合系数提取算法,参考滤波器综合理论,设计并加工了工作频段为1.3～1.45 GHz的开环微带谐振可切换带宽的可调频率带通滤波器。测试结果表明,在整个工作频段内,3 dB 带宽在切换前后分别为120 MHz、100 MHz 和80 MHz,对应的插入损耗各是-2.9 dB、-2.4 dB、-2.6 dB,测试结果与仿真结果吻合良好。该滤波器具有结构简单、加工难度低、体积小、馈电控制简单等优点。     

Design of a 2-pole LTCC filter for wireless communications

This letter outlines the designing and manufacture of a miniaturized bandpass filter realized by low-temperature cofired ceramic (LTCC) technology for wireless products. The bandpass filter with a central frequency of 1950 MHz and a 5% passband is designed as a three-dimensional (3-D) structure based on lumped components. The design technique based on cascading overall circuit into blocks and computer-aided design of electrical circuit is presented. Experimental measurements were compared with modeling. The insertion losses in the passband (100 MHz) were less than 2 dB and the attenuation more than 20 dB in the stopband. The area occupied by the filter is 6.6/spl times/6.6/spl times/0.836 mm/sup 3/ in plane.     

基于LTCC的超宽带巴伦滤波器小型化设计

该文设计了一种基于低温共烧陶瓷(LTCC)技术的小型化超宽带巴伦(Balun)滤波器。该巴伦滤波器由一个五阶带通滤波器和基于Marchand巴伦改进型巴伦级联组成,带通滤波器采用耦合谐振式的设计方法,设计成宽带高抑制巴伦滤波器,在二阶、三阶和四阶谐振之间创新采用电感级联的拓扑结构,使相对带宽在48%以上。巴伦输入与输出之间的耦合采用一种并联堆叠式耦合螺旋传输线,增强了传输线之间的耦合,并拓宽了巴伦的带宽。结果表明,该巴伦滤波器通带为1.71～2.76 GHz,插损均小于2.3 dB;在50～669 MHz,抑制大于35 dB;在669～1 245 MHz,抑制大于17 dB;在3 205～3 400 MHz,抑制大于27 dB;在3 400～6 000 MHz,抑制均大于30 dB。两个输出端口信号的相位差和幅度差分别为180°±15°(1 710～2 340 MHz)、180°±10°(2 500～2 760 MHz)和±1.0 dB,具有较高的通用性和良好的应用市场。     

A 50.8–53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- $mu$m CMOS

A 50.8-53-GHz clock generator with a quadruplicate-harmonic-locked phase detector (PD) is presented to achieve a low spur and a low reference frequency. The proposed quadruplicate-harmonic-locked PD, a low-voltage Colpitts voltage-controlled oscillator, and a wide-range divide-by-2 divider are also presented. This clock generator has been fabricated in a 0.13-mum process. The measured reference spur is -59.88 dBc at 51.02 GHz with an input reference frequency of 199.3 MHz. The area is 0.93 mm times 1 mm with the on-chip loop filter and pads. It dissipates 87 mW without buffers from a 1.5-V supply.     

片上自动调谐的可编程有源RC滤波器

研制了一款可编程6阶巴特沃斯有源RC滤波器.为提高滤波器中运算放大器的增益带宽积,设计了一种新型的前馈补偿运算放大器.为消除工艺偏差和环境变化对截止频率的影响,设计了一种片上数字控制频率调谐电路,并采用TSMC 0.18 μm CMOS工艺进行了流片.滤波器采用低通滤波结构,测试结果表明,3 dB截止频率为1～32 MHz,步进1 MHz,带内增益0 dB,带内纹波0.8 dB,2倍带宽处带外抑制不小于24 dBc,5倍带宽处带外抑制不小于68 dBc,滤波器等效输入噪声为340 nV/√Hz@1MHz,调谐误差为±3％.滤波器裸芯片面积0.87 mm×1.05 mm.采用1.8V电源电压,滤波器整体功耗小于20 mW.