一种适用于内嵌时钟串行链路的5Gbps小面积CDR

本文提出了一种支持多标准的具有系数可调的均衡器和宽跟踪能力的时钟数据恢复电路。基于对系统参数和一阶 bang-bang 时钟数据恢复电路的环路特性分析,推导出电路设计参数。考虑到抖动性能,追踪能力以及芯片面积,文中采用了一阶数字滤波器和6-bit DAC以及高线性度的相位插值器实现了高相位调整精度和小面积的时钟恢复电路,同时该结构实现了±2200ppm的频偏跟踪能力,使得该结构适用于不同源的高速串行传输系统,尤其是内嵌时钟结构。该设计已经在55nm CMOS工艺上流片验证,测试结果显示符合误码率的要求以及抖动容忍规范。该测试芯片整体面积是0.19mm2,其中时钟恢复电路只占0.0486mm2 而且该电路工作在5Gbps,供电电压为1.2V时,只消耗30mW。     

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector

This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mum CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplifiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 2³¹-1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10^-15 and the jitter tolerance is 0.5UIpp, which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 psrms at a 155.52MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies     

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance and low jitter. To design the CDR using a PLL that includes a decision circuit with a certain phase margin affecting the pull-in performance, we derived a simple expression for the pull-in range of the PLL, which we call the "limited pull-in range," and used it for the pull-in performance evaluation. The method allows us to quickly and easily compare the pull-in performance of a conventional PLL with a full-rate clock and a PLL with a half-rate clock, and we verified that the half-rate PLL is advantageous because of its wider frequency range. For verification of the method, we fabricated a half-rate CDR with a 1:16 DEMUX IC using commercially available Si bipolar technology with f/sub T/=43 GHz. The half-rate clock technique with a linear phase detector, which is adopted to avoid using the binary phase detector often used for half-rate CDR ICs, achieves good jitter characteristics. The CDR IC operates reliably up to over 15 Gb/s and achieves jitter tolerance with wide margins that surpasses the ITU-T specifications. Furthermore, the measured jitter generation is less than 0.4 ps rms, which is much lower than the ITU-T specification. In addition, the CDR IC can extract a precise clock signal under harsh conditions, such as when the bit error rate of input data is around 2/spl times/10/sup -2/ due to a low-power optical input of -24 dBm.     

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/sSONET application

An integrated 10 Gb/s clock and data recovery (CDR) circuit is fabricated using SiGe technology, It consists of a linear-type phase-locked loop (PLL) based on a single-edge version of the Hogge phase detector, a LC-tank voltage-controlled oscillator (VCO) and a tri-state charge pump. A PLL equivalent model and design method to meet SONET jitter requirements are presented. The CDR was tested at 9.529 GB/s in full operation and up to 13.25 Gb/s in data recovery mode. Sensitivity is 14 mV_pp at a bit error rate (BER)=10^-9 . The measured recovered clock jitter is less than 1 ps RMS. The IC dissipates 1.5 W with a -5 V power supply     

1.25Gbps串并并串转换接收器的低抖动设计

对1.25Gbps应用于千兆以太网的低抖动串并并串转换接收器进行了设计,应用了带有频率辅助的双环时钟数据恢复电路,FLL扩大了时钟数据恢复电路的捕捉范围。基于三态结构的鉴频鉴相从1.25Gbps非归零数据流中提取时钟信息,驱动一个三级的电流注入环形振荡器产生1.25GHz的低抖动时钟。从低抖动考虑引入了均衡器。该串并并串转换接收器采用TSMC0.35μm2P3M3.3V/5V混合信号CMOS技术工艺。测试结果表明了输出并行数据有较好的低抖动性能:1σ随机抖动(RJ)为7.3ps,全部抖动(TJ)为58mUI。     

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.     

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.     

A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS

A clock and data recovery (CDR) architecture featuring a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding fixed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt-peaking and capacitance coupling. The monolithic CDR implemented in 0.13-$muhbox m$CMOS shows 1.7 times wider phase linear response region of 0.56UI than that of a conventional CDR. It operates at 12.5-Gb/s with PRBS$2 ^31 -1$input data. Measurements show large jitter tolerance of over 0.5 UIpp for 4-8 MHz jitter frequency as well as jitter transfer characteristics independent on input-jitter amplitudes of 0.1, 0.3, and 0.5 UIpp.     

Jitter analysis and modeling of a 10 Gbit/s SerDes CDR and jitter attenuation PLL

Jitter analysis and a linear model is proposed in this paper which predicts the characteristics of serial-deserial(SerDes) clock and data recovery circuit,and the characteristics include jitter transfer,jitter tolerance and jitter generation are particularly analyzed.The simulation results of the clock data recovery(CDR) model show that the jitter specifications exceed the mask of ITU-T optical transport network(OTN) G.8251 recommendations.The whole systems are validated by 9.95-11.5 Gbit/s CDR and the jitter attenuation phase locked loops(PLL) circuits using TSMC 65 nm CMOS technology.     

一种环路带宽自适应调整的时钟数据恢复电路

针对SONTE OC-192、PCIE3.0、USB3.2等协议在串行时钟数据恢复时对抖动容限、环路稳定时间的要求,提出了一种环路带宽自适应调整、半速率相位插值的时钟数据恢复电路(CDR)。设计了自适应控制电路,能适时动态调整环路带宽,实现串行信号时钟恢复过程中环路的快速稳定,提高了时钟数据恢复电路抖动容限。增加了补偿型相位插值控制器,进一步降低了数据接收误码率。该CDR电路基于55 nm CMOS工艺设计,数据输入范围为8～11.5 Gbit/s。采用随机码PRBS31对CDR电路的仿真测试结果表明,稳定时间小于400 ns,输入抖动容限大于0.55UI@10 MHz,功耗小于23 mW。     

An all-digital semi-blind clock and data recovery system

This paper presents a digitally intensive semi-blind clock and data recovery (SBCDR) system. The paper covers the theory, analysis, and system level simulation of this SBCDR. The proposed CDR is tailored to target the optical network standard OC-192. The SBCDR can provide the required jitter tolerance (JTo), and still provide enough jitter filtering to achieve the jitter transfer (JTr) requirements. Also, the recovered clock achieves a low jitter generation (JG) of 0.01 UI_rms and 0.0064 UI_rms for both the wide-band and high-band jitter filters defined by the standard. The proposed SBCDR provides two advantages over typical SBCDRs and PLL-based CRDs that target OC-192. First, the digitally intensive nature provides a scalable and process tolerant design. Second, the architecture provides a CDR that can pass all three jitter performance metrics, without the aid of an external clean-up phase locked loop (PLL) or a high performance clock multiplication unit (CMU) typically required by OC-192 transceivers. By utilizing a circular representation for the phase calculation in the over-sampling clock and data recovery (OSCDR), extensive pipe-lining in the implementation and higher data rate tolerance can be achieved. The simulation results of the proposed SBCRD agree closely with theoretical results.     

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 2/sup 31/ - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.     

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging delay locked loop and a rate-detection circuit is presented. It can achieve wide range and low jitter operation. A duty-cycle-insensitive phase detector is also proposed to mitigate the dependency on clock duty cycle variations. The experimental prototype has been fabricated in a 0.25-/spl mu/m 1P5M CMOS technology and occupies an active area of 2.89 mm/sup 2/. The measured CDR could operate from 125 Mb/s to 2.0 Gb/s with a bit error rate better than 10/sup -12/ from a 2.5-V supply. Over the entire operating frequency range, the maximum rms jitter of the recovered clock is less than 4 ps.     

一种全速率线性25Gb/s时钟数据恢复电路

面向高速光通信系统的应用,提出了一种全速率线性25Gb/s时钟数据恢复电路(Clock and Data Recovery Circuit,CDRC)。CDRC采用了混频器型线性鉴相器和自动锁频技术来实现全速率时钟提取和数据恢复。在设计中没有使用外部参考时钟。基于45nm CMOS工艺,该CDR电路从版图后仿真结果得到:恢复25Gb/s数据眼图的差分电压峰峰值V_pp和抖动峰峰值分别为1.3V和2.93ps;输出25GHz时钟的差分电压峰峰值V_pp和抖动峰峰值分别为1V和2.51ps,相位噪声为-93.6dBc/Hz@1MHz。该芯片面积为1.18×1.07mm²,在1V的电源电压下功耗为51.36mW。     

Multi-gigabit-rate clock and data recovery based on blind oversampling

This article addresses issues with designing a blind oversampling clock and data recovery unit (CDR) that meets jitter tolerance specifications. Asymptotic limits on jitter tolerance are derived assuming ideal phase detection based on a priori statistics of the received signal, proving that the coarse timing resolution of blind oversampling CDR relies on a phase detection algorithm that makes good estimates of the signal's statistics with a finite number of discrete samples and at reasonable hardware costs. The statistical simulation methodology outlined here enables quick verification of the bit error rate and comparisons between the jitter tolerances of various blind oversampling CDR architectures.     

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.     

A 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits

A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2³¹‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.     

10 GHz full-rate clock and data recovery circuit in 0.18 /spl mu/m CMOS without external reference clock

The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 /spl mu/m digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mV/sub pp/ pseudorandom bit Sequence input data of length 2/sup 31/-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.