Characteristics of sub-100-nm p+/n junctions fabricatedby plasma immersion ion implantation

Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p⁺/n diodes with junction depths below 100 nm. SiF₄ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF₃ is implanted. Ultrashallow p⁺/n junctions are formed by annealing at 1060 °C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm ² in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 μs     

Low-Complexity Full-Melt Laser-Anneal Process for Fabrication of Low-Leakage Implanted Ultrashallow Junctions

Good-quality ultrashallow n ⁺ p junctions are formed using 5-keV amorphizing As⁺ implantations followed by a single-shot excimer laser anneal for dopant activation. By using an implant that is self-aligned to the contact windows etched in an oxide isolation layer, straightforward processing of the diodes is achieved with postimplantation processing temperatures kept below 400°C. A possible source of junction leakage at the perimeter caused by dip-etch enlargement of the contact window, also confirmed by transmission electron microscopy (TEM) analysis, is identified, and diode performance is improved by increasing the junction/contact window overlap. The optimum performance in terms of low leakage, shallow junctions, and low resistivity is achieved for 30° tilted implants and by applying a thin laser-reflective aluminum layer. This work isolates the minimum requirements for achieving low-leakage diode characteristics.     

The reverse anneal of junction characteristics in forming shallow p+-n junction by BF2+ implantation intothin Co films on Si substrate

Silicided shallow p⁺-n junctions, formed by BF₂ ⁺ implantation into thin Co films on Si substrates and subsequently annealed, showed a reverse anneal of junction characteristics in the temperature range between 550 and 600°C. The reverse anneal means behavior showing degradation of the considered parameters with increasing annealing temperature. A higher implant dosage caused a more distinct reverse anneal. The reverse anneal of electrical characteristics was associated with the reverse anneal of substitutional boron. A shallow p⁺-n junction with a leakage current density lower than 3 nA/cm₂, a forward ideality factor of better than 1.01, and a junction depth of about 0.1 μm was achieved by just a 550°C anneal     

Determination of shallow defect levels using thermally stimulated current in implant-layer/substrate junctions of GaAs MESFETs

Thermally stimulated current measurements have been made using test samples of np- junctions formed by ion-implantation on semi-insulating substrates. The results of measurements demonstrate that in spite of a high-value series resistance of the substrate these junctions can be used for rapid identification of shallow electron traps. The trap energy levels determined for the test samples are at 0.13eV and 0.29eV below the bottom of the conduction band possibly arising due to implantation damage or induced by thermal processes.     

Impact of Ge implantation on the electrical characteristics of TiSi2 p+/n shallow junctions with an a-Si (or apoly-Si) buffer layer

A new technology for forming a titanium-silicide shallow junction by combining germanium implantation with an amorphous-silicon (or a poly-silicon) buffer layer has been proposed for MOSFETs. The use of a buffer layer between Ti and Si can avoid the consumption of bulk-silicon and the recession of TiSi₂ film into the source/drain junctions during the silicidation process. In this study, the important role of germanium-implantation on the formation of TiSi₂ contacted p⁺/n junctions was examined. After subsequent implantation of Ge⁺ and B⁺ into the TiSi₂ film, samples were annealed at different temperatures to form p ⁺/n junctions and C54-TiSi₂. Since the penetration of titanium atoms was suppressed due to the germanium-implantation, the periphery leakage and the generation leakage were improved and TiSi₂/Si interfaces were even smooth. Therefore, p⁺/n junctions with a very low leakage current (0.192 nA/cm ² at -5 V) and an excellent forward ideality factor (n≈1.002) can be obtained. From the secondary ion mass spectrometry (SIMS) analysis, the junction depth is 400     

Device-grade ultra-shallow junctions fabricated with antimony

Extremely shallow, below ∼80 nm, n+ junctions fabricated with antimony have been analytically and electrically investigated. It is shown that by the use of antimony one can reach sheet resistivity/ shallowness combinations that are superior to those achievable with arsenic. The leakage of these junctions was found to be sufficiently low to allow VLSI applications. These investigations indicate that below a certain junction depth antimony should be the dopant of preference.     

Si~+/B~+双注入单晶硅的快速热退火

用四探针法、扩展电阻法、背散射沟道谱和二次离子质谱等测试分析手段研究了Ｓｉ＋ ／Ｂ＋ 双注入单晶硅的快速热退火行为。结果表明：Ｓｉ＋ 预非晶化注入能有效地抑制注入硼原子的沟道效应;快速热退火Ｓｉ＋ ／Ｂ＋ 注入样品,其注入损伤基本消除,残留二次缺陷少,硼原子电激活率高;优化与控制快速热退火条件和Ｓｉ＋ ／Ｂ＋ 注入参数,制备出了电学特性优良的浅ｐ＋ ｎ 结,其二极管反偏漏电流仅为１．９ ｎＡ·ｃｍ － ２（－ １．４Ｖ）。     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

The formation of shallow low-resistance source—Drain regions for VLSI CMOS technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-µm transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p⁺regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n⁺and p⁺junction depths are 0.22 µm and of 8 Ω/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Al/W/TiNx/TiSiy/Si barrier technology for1.0-μm contacts

A reliable contact diffusion barrier has been successfully formed by sintering in nitrogen a physically sputtered W/Ti bilayer. After a 650°C furnace anneal, a TiN_x/TiSi_y layer on contact with the silicon substrate was formed beneath the overlying W. No reaction between N₂ and W was observed. Arsenic implanted in the silicon substrate tended to retard the silicidation of titanium. Substantial redistribution of both B and As across the silicide layer was also observed during the contact sintering process. The 1.0-μ contacts fabricated with the Al/W/TiN_x/TiSi_y/Si barrier technology exhibited low and tightly distributed contact resistivities (less than 10^-6 Ω-cm²). No excessive leakage of the shallow junctions was observed even after thermally stressing the sample at 400°C for 8 h     

A silicidation-induced process consideration for forming scale-downsilicided junction

A process consideration for forming silicided shallow junctions, arising from silicidation process, has been discussed. The CoSi₂ shallow p⁺n junctions formed by various schemes are characterized. The scheme that implants BF₂⁺ ions into thin Co films on Si substrates and subsequent silicidation yields good junctions, but the problems about the dopant drive-in and knock-on of metal deeply degrade this scheme. In the regime that implants the dopant into Si and then Co deposition, however, a large perimeter leakage of 0.1 nA/cm is caused. Generation current, associated with a defect-enhanced diffusion of Co in Si during silicidation, dominates the leakage. A high-temperature pre-activation prior to Co deposition reduces the perimeter leakage to 0.038 nA/cm, but which deepens the junctions     

Various effects of silicidation on shallow p+ junctionsformed by BF2+ implantation into thin poly-Sifilms on Si substrates

Various effects of silicidation on shallow p⁺ n junctions formed by the scheme that implants BF₂⁺ ions into thin poly-Si films on Si substrates are described. A post-Ni silicidation just slightly improves the preformed junctions of the annealed sample. However, as the sample is first deposited with thin Ni films after the implantation and then annealed, the resulting junctions are much better than the preformed ones. Moreover, as the sample is deposited with Ti films, the resultant junctions are just slightly better the preformed ones     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

Material and electrical properties of ultra-shallow p+-njunctions formed by low-energy ion implantation and rapid thermalannealing

A study of low-energy ion implantation processes for the fabrication of ultrashallow p⁺-n junctions is presented. The resulting junctions are examined in terms of four key parameters: defect annihilation, junction depth, sheet resistance, and diode reverse leakage current. In the realm of very-low-energy ion implantation, Ge preamorphization is found to be largely ineffective at reducing junction depth, despite the fact that the as-implanted boron profiles are much shallower for preamorphized substrates than for crystalline substrates. Transmission electron microscopy (TEM) analysis of residual defects after rapid thermal annealing (RTA) reveals that the use of either a preamorphization implant or the implantation of BF₂ as a B source results in residual damage which requires higher RTA temperatures to be removed. A reasonable correlation is observed between residual defect density observed via TEM and junction leakage current. It is concluded that the key to an optimized low-energy implantation process for the formation of ultrashallow junctions appears to be the proper selection of preamorphization and annealing conditions relative to the dopant implant energy     

双掺硅单晶及其P-N结研究

按照一定的掺杂比例制备了一种双掺硅单晶。单晶片经热处理后形成的P-N结具有结深浅、均匀、杂质浓度分布不同于扩散结和离子注入结等特点。本工作对P-N结形成的规律进行了理论和实验研究,结果十分吻合。对P-N结的基本特性和光学性能的研究说明:这种双掺硅形成的P-N结有可能用于制作光电器件、集成电路、太阳能电池和某些特殊器件。结果还有助于对硅表面反型的机构及界面问题的进一步认识。这项研究工作还提供了一种新的获取P-N结的工艺方法,这种方法在制造某些器件和集成电路时,工艺将大为简化。     

Systematic study of shallow junction formation on germanium substrates

Published results on Ge junctions are benchmarked systematically using R_S-X_J plots. The electrical activation level required to meet the ITRS targets is calculated. Additionally, new results are presented on shallow furnace-annealed B junctions and shallow laser-annealed As junctions. Co-implanting B junctions with F is shown to degrade junction properties.     

The Formation of Shallow Low-Resistance Source-Drain Regions for VLSI CMOS Technologies

As a result of MOS device scaling, very shallow source-drain structures are needed to minimize short-channel effects in 1-/spl mu/m transistors. This can be readily achieved with highly doped arsenic regions for NMOS devices but is more difficult using boron for PMOS devices. In addition, shallow junctions suffer from inherently high sheet resistances due to dopant solid solubility limitations. This paper proposes an improved CMOS source-drain technology to overcome both these problems. The technique employs amorphizing silicon implants prior to dopant implantation to eliminate ion channeling and platinum silicidation to substantially reduce sheet resistance. Counterdoping of the p/sup +/ regions by high-concentration arsenic implantation is used to enable both NMOS and PMOS devices to be manufactured with only one photolithographic masking operation. Using this technique, n/sup +/ and p/sup +/ junction depths are 0.22 /spl mu/ and of 8 /spl Omega/sq. sheet resistance. By creating oxide sidewalls on gate conductors, polysilicon can be silicided simultaneously with diffusions. Results of extensive materials analysis are discussed in detail. The technique has been incorporated into a VLSI CMOS process schedule at our laboratories.     

Shallow-junction diode formation by implantation of arsenic andboron through titanium-silicide films and rapid thermal annealing

The performance of diodes fabricated on n-type and p-type Si substrates by implanting As or B through a low-resistivity titanium-silicide layer is discussed. The effects of varying the implant dose, energy, and postimplant thermal treatment were investigated. After implantation, a rapid thermal anneal was found to remove most of the implant damage and activate the dopants, which resulted in n⁺-p and p⁺-n junctions under a low-resistivity silicide layer. The n⁺-p junctions were as shallow as 1000 Å with reverse leakage currents as low as 5.5 μA/cm². A conventional furnace anneal resulted in a further reduction of this leakage. Shallow p⁺-n junctions could not be formed with boron implantation because of the large projected range of boron ions at the lowest available energy. Ti silicide films thinner than 600 Å exhibited a sharp rise in sheet resistivity after a furnace anneal, whereas thicker films exhibited more stable behavior. This is attributed to coalescence of the films. High-temperature furnace annealing diffused some of the dopants into the silicide film, reducing the surface concentrations at the TiSi₂ -Si interface     

Short channel characteristics of Si MOSFET with extremely shallowsource and drain regions formed by inversion layers

The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFET's are experimentally investigated. These extremely shallow junctions are realized in MOSFET's with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFET's whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 μm while punchthrough is suppressed down to 0.07 μm, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects     

Forming of Very Shallow Junction for S/D Extension in Deep Sub-Micron CMOS Devices

Very shallow junctions for S/D extension in deep sub-micron CMOS devices are required to suppress the short channel effect as devices scaling down, and the surface concentrations (N,) of these junctions need to be kept in a higher value to reduce the series resistance of the lightly doped drain structure. But it is very difficult for the conventional ion implantation to meet the requirement above. This article presents the results of forming very shallow and ultrashallow junctions used in 0.25 micron and 0.10 micron CMOS devices respectively with low energy implantation (LEI) and pre-amorphization implantation plus low energy implantation (PAI+LEI). The LEI was performed on the modified normal ion-imptantor (IM-200M). Using LEI only the minimum junction depth,is 61nm for NMOS and 57nm for PMOS (Nsub=1×1018cm-3) respectively after 1000℃ RTA and both Ns are above 3×1019cm-3 While using Ge PAI+LEI,under the optimized processing condition,the junction depth of 58nm for NMOS and 42nm for PMOS are obtained,with the leakage current density being 4nA/cm2.