Fabrication and thermal evaluation of silicon on diamond wafers

Silicon on diamond (SOD) is proposed as a superior alternative to conventional silicon on insulator (SOI) technology for silicon-based electronics. In this paper, we present a novel SOD structure in which the active Si layer is in direct contact with a thick, highly oriented diamond (HOD) layer that is directly attached to a heat sink. In contrast to the earlier work,^1,2 the diamond film is relatively thick (∼70 μm), free standing, and close to single crystalline, thus possessing much greater thermal conductivity and no limitation of the Si backing wafer. Two different fabrication schemes are investigated: (1) direct growth, where the Si-device layer makes contact with the nucleation side of the diamond layer; and (2) wafer fusion, where the Si device layer makes a direct contact with the diamond growth surface. Thermal evaluation was performed using metallic microheaters. These studies clearly showed more than one order of magnitude better thermal management properties of diamond with respect to Si and SOI.     

通过优化额外的硼注入工艺减小STI对SONOS存储器的影响

The influence of shallow trench isolation (STI) on a 90 nm polysilicon–oxide–nitride–oxide–silicon structure non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.     

一种基于倾斜悬臂梁的高性能硅微陀螺

This paper presents a novel structure for improving the stability and the mechanical noise of micromachined gyroscopes. Only one slanted cantilever is used for suspension in this gyroscope, so the asymmetry spring and the thermal stress, which most micromachined gyroscopes suffer from, are reduced. In order to reduce the mechanical noise, the proof masses are designed to be much larger than in most micromachined gyroscopes. The gyroscope chip is sealed at 0.001 Pa vacuum. A gyroscope sample and its read-out circuit are fabricated. The scale factor of this gyroscope is measured as 57.6 mV/（deg/sec） with a nonlinearity better than 0.12% in a measurement range of ±100 deg/sec. The short-term bias stability in 20 min is 60 deg/h.     

Structural Un-uniformity and Electrical Anisotropy of μc-Si:H Films

Structural un-uniformity and electrical anisotropy of μc-Si∶H film are investigated in this paper. It is found that the structure of μc-Si∶H film along the direction perpendicular to the substrate is not uniform, which is modulated by film thickness. In addition, there is a dark conductivity anisotropy along the direction parallel(σ∥) and perpendicular(σ⊥)to the substrate in μc-Si∶H film. The reasons for such an property of μc-Si∶H film and the effect of oxygen contamination are analyzed.     

一种新型压阻值理论计算方法

A novel algorithmic method, based on the different stress distribution on the surface of thin film in an SOI microstructure, is put forward to calculate the value of the silicon piezoresistance on the sensitive film. In the proposed method, we take the Ritz method as an initial theoretical model to calculate the rate of piezoresistance ΔR/R through an integral （the closed area Ω where the surface piezoresistance of the film lies as the integral area and the product of stress σ and piezoresistive coefficient π as the integral object） and compare the theoretical values with the experimental results. Compared with the traditional method, this novel calculation method is more accurate when applied to calculating the value of the silicon piezoresistance on the sensitive film of an SOI pieoresistive pressure sensor.     

Optimization of saturation current density of PECVD SiN coated phosphorus diffused emitters using neural network modeling

Emitter surface passivation by low temperature plasma enhanced chemical vapor deposition (PECVD) silicon nitride is investigated and optimized in this paper. We have found that the saturation current density of a 90±10 μ/sq phosphorus diffused emitter with N_s ≈3 x 10¹⁹ and X_j ≈0.3 μm can be lowered by a factor of eight by appropriate PECVD silicon nitride deposition and photoassisted anneal. PECVD silicon nitride deposition alone reduces the emitter saturation density (J_oe) by about a factor of two to three, and a subsequent photoanneal at temperatures ≥350°C reduces J_oe by another factor of three. In spite of the larger flat band shift for direct PECVD silicon nitride coating, the silicon nitride induced surface passivation is found to be about a factor of two inferior to the thermal oxide plus PECVD silicon nitride passivation due to higher interface state density at the SiN/SiO₂ interface compared to SiO₂/Si interface. A combination of statistical experimental design and neural network modeling is used to show quantitatively that lower radio frequency power, higher substrate temperature, and higher reactor pressure during the PECVD deposition can reduce the J_oe of the silicon nitride coated emitter.     

多层压电结构中声表面波特性的计算

The propagation properties of the surface acoustic waves(SAWs) in a ZnO-SiO2-Si multilayered piezoelectric structure are calculated by using the recursive asymptotic method.The phase velocities and the electromechanical coupling coefficients for the Rayleigh wave and the Love wave in the different ZnO-SiO2-Si structures are calculated and analyzed.The Love mode wave is found to be predominantly generated since the c-axis of the ZnO film is generally perpendicular to the substrate.In order to prove the calculated results,a Love mode SAW device based on the ZnO-SiO2-Si multilayered structure is fabricated by micromachining,and its frequency responses are detected.The experimental results are found to be mainly consistent with the calculated ones,except for the slightly larger velocities induced by the residual stresses produced in the fabrication process of the films.The deviation of the experimental results from the calculated ones is reduced by thermal annealing.     

从电路特性方面考虑而提出的SOI-DTMOS新结构

The performance of a partially depleted silicon-on-insulator （PDSO1） dynamic threshold MOSFET （DT- MOS） is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOl DTMOSFET structure （drain/source-on-local-insulator structure） is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.     

Effects of vacancy structural defects on the thermal conductivity of silicon thin films

Vacancy structural defect effects on the lattice thermal conductivity of silicon thin films have been investigated with non-equilibrium molecular dynamics simulation.The lattice thermal conductivities decrease with increasing vacancy concentration at all temperatures from 300 to 700 K.Vacancy defects decrease the sample thermal conductivity,and the temperature dependence of thermal conductivity becomes less significant as the temperature increases.The molecular dynamics result is in good agreement with the theoretical analysis values obtained based on the Boltzmann equation.In addition,theoretical analysis indicates that the reduction in the lattice thermal conductivity with vacancy defects can be explained by the enhanced point-defect scattering due to lattice strain.     

Design of MEMS C-Band Microstrip Antenna Array Based on High-Resistance Silicon for Intelligent Ammunition

In recent years, microstrip antennas have been more widely applied in satellite communications, mobile phones, unmanned aerial vehicle (UAV), and weapons. A micro-electro-mechanical systems-based (MEMS-based) high-resistance silicon C-band microstrip antenna array has been designed for the intelligent ammunition. The center frequency is 4.5 GHz. A cavity has been designed in substrate to reduce the dielectric constant of silicon and high-resistance silicon has been used as the material of substrate to improve the gain of antenna. It is very easy to be manufactured by using MEMS technology because of the improved structure of the antenna. The results show that the gain of the antenna is 8 dB and voltage standing wave ratio (VSWR) is less than 2 by the analysis and simulation in high frequency structure simulator (HFSS).     

Silicon Nitride Films Deposited by RF Sputtering for Microstructure Fabrication in MEMS

In the present work, we report silicon nitride films deposited by a radio- frequency (RF) sputtering process at relatively low temperatures (<260°C) for microelectromechanical system (MEMS) applications. The films were prepared by RF diode sputtering using a 3-inch-diameter Si₃N₄ target in an argon ambient at 5 mTorr to 20 mTorr pressure and an RF power of 100 W to 300 W. The influence of the film deposition parameters, such as RF power and sputtering pressure, on deposition rate, Si-N bonding, surface roughness, etch rate, and stress in the films was investigated. The films were deposited on single/double-side polished silicon wafers and transparent fused-quartz substrates. To explore the RF-sputtered silicon nitride film as a structural material in MEMS, microcantilever beams of silicon nitride were fabricated by bulk, surface, and surface-bulk micromachining technology. An RF-sputtered phosphosilicate glass film was used as a sacrificial layer with RF-sputtered silicon nitride. Other applications of sputtered silicon nitride films, such as in the local oxidation of silicon (LOCOS) process, were also investigated.     

Fabrication of low-stress dielectric thin-film for microsensorapplications

A method of fabricating low-stress dielectric thin film as the supporting material of micromachined devices is reported. The film is processed by post thermal oxidation of silicon-rich nitride (SN) deposited on a silicon substrate by LPCVD. Due to the compensation on the nitride by its top oxide, an ultra-low residual stress less than 10 MPa can be obtained with a proper oxidation scheme. Characteristics of the oxidized nitride were analyzed by Auger electron spectroscopy (AES) and ellipsometry. Large floating membranes of 4×4 cm² and 400-nm thick can be made by this method with TMAH etching     

SIMS study of silicon oxynitride prepared by oxidation of silicon-rich silicon nitride layer

We proposed a novel process for fabrication silicon oxide–oxynitride–oxide structure for ULSI device applications. By deposition of silicon-rich silicon nitride and then following a thermal oxidation process, a good oxynitride layer was obtained. Secondary ion mass spectroscopy (SIMS) study reveals that the hydrogen content of nitride film at the interface can be reduced by more than 40% when compared to stoichiometric nitride. With this method, high nitrogen content oxynitride and smoother oxynitride/oxide interfaces result in the reduction of the interface charge trapping remarkably.     

High quality silicon nitride deposited by Ar/N2/H2/SiH4 high-density and low energy plasma at low temperature

The high-quality PECVD silicon nitride has been deposited by high-density and low-ion-energy plasma at 400 °C and the effect of the process parameters, such as silane and nitrogen flow rate, pressure, on its structure and electrical properties has been investigated. The experimental results show that silane flow rate is the most sensitive parameter for determining deposition rate and N/Si atomic ratio of silicon nitride in the range of process parameters employed. The change of nitrogen flow rate leaded to slightly change in deposition rate, however, it effects significantly on the refractive index or densification of silicon nitride. With the addition of hydrogen gas in plasma, the hysteresis of C-V characteristics of MIS structure decreases from 0.4 to 0.1 V. The moderate increment of ion energy makes further reduction in the hysteresis of C-V characteristics of MIS from 0.1 V to below 0.05 V. The interface trap density of 6.2×10¹⁰ (ev⁻¹ cm^-2), deduced from the high frequency and quasistatic C-V characteristics of the MIS structure, is about the same as that of LPECVD silicon nitride deposited at the range of 750-850 °C. The stoichiometric silicon nitride of excellence electric and structural properties is obtained by Ar/N₂/H₂/SiH₄ high-density and low ion energy plasma.     

Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides

Dual layer dielectrics have been formed by remote PECVD deposition of ultra-thin (0.4–1.2 nm) nitrides onto thin thermal oxides grown on n-type Si(100) substrates. Activation of boron-implanted p+ polycrystalline silicon gate electrodes was accomplished by a high temperature anneal, 1–4 min at 1000°C. Boron penetration through the dielectric film to the n-type substrate was investigated by performing a quasi-static C–V analysis and monitoring the flatband voltage shift. Boron penetration was effectively stopped by a 0.8 nm nitride film, and partially stopped by a 0.4 nm nitride film. In addition, the charge to breakdown as monitored by the Q_bd value to 50% cumulative failure was highest for the device with the 0.8 nm top nitride, and decreased significantly in the thermal oxide. However there were essentially no differences in the mid-gap interface state densities, D_it, between oxide and nitride/oxide gate dielectric structures with Al gate. It is concluded that the 0.8 nm of plasma nitride was sufficient to block boron atom out-diffusion from a heavily implanted p+ poly-silicon gate electrode under the conditions of an aggressive implant activation anneal to improve the dielectric reliability.     

The metal-insulator-semiconductor-switch (MISS) device using thermal nitride film as the tunneling insulator

Silicon thermal nitride films grown by using direct thermal nitridation of silicon have been used as a tunneling insulator in the metal-insulator-semiconductor-switch (MISS) device. This paper has shown that better uniformity and controllability of the MISS characteristics can be easily obtained by using thermal nitride film as a tunneling insulator when compared to those using conventional thermal oxide film. The superior merits of using silicon thermal nitride film are mainly due to the fact that direct thermal nitridation of silicon in ammonia gas exhibits much lower growth rate and unique self-limiting growth. Moreover, the higher structure density of the as-grown thermal nitride film may provide higher endurance for the MISS device in integrated-circuit applications. In addition, the MISS devices operated at lower voltage (< 5 V) have been fabricated and their characteristics are discussed.     

Textured silicon surface passivation by high‐rate expanding thermal plasma deposited SiN and thermal SiO2/SiN stacks for crystalline silicon solar cells

Expanding thermal plasma (ETP) deposited silicon nitride (SiN) with optical properties suited for the use as antireflection coating (ARC) on silicon solar cells has been used as passivation layer on textured monocrystalline silicon wafers. The surface passivation behavior of these high‐rate (>5 nm/s) deposited SiN films has been investigated for single layer passivation schemes and for thermal SiO₂/SiN stack systems before and after a thermal treatment that is normally used for contact‐firing. It is shown that as‐deposited ETP SiN used as a single passivation layer almost matches the performance of a thermal oxide. Furthermore, the SiN passivation behavior improves after a contact‐firing step, while the thermal oxide passivation degrades which makes ETP SiN a better alternative for single passivation layer schemes in combination with a contact‐firing step. Moreover, using the ETP SiN as a part of a thermal SiO₂/SiN stack proves to be the best alternative by realizing very low dark saturation current densities of <20 fA/cm² on textured solar‐grade FZ silicon wafers and this is further improved to <10 fA/cm² after the anneal step. Optical and electrical film characterizations have also been carried out on these SiN layers in order to study the behavior of the SiN before and after the thermal treatment. Copyright © 2008 John Wiley & Sons, Ltd.     

The effect of pulsed laser annealing on the nickel silicide formation

The pulsed laser annealing (PLA) is used to assist nickel silicide transformation for Schottky barrier height reduction and tensile strain enhancement and the effect of different laser power are investigated. In this report, a two-step annealing process which combine the conventional rapid thermal annealing with pulsed laser annealing is proposed to achieve a smooth silicon-rich NiSi_x interfacial layer on (1 0 0) silicon. With optimized laser energy, a 0.2 eV Schottky barrier height (SBH) modulation is observed from Schottky diode electrical characterization. Furthermore, PLA provides sufficient effective temperature during silicidation which also lead to increased tensile stress of silicide film than the two-step RTA silicide is also investigated. The SBH modulation and tensile stress enhancement benefits of PLA silicidation are considered as an alternative to the conventional rapid thermal annealing for ultra-scaled devices performance enhancement.     

Science and prospects for non-stoichiometry in dielectrics

Si nanodots (NDs) were produced in a silicon-rich dielectric matrix by plasma-enhanced chemical vapor deposition. After rapid thermal annealing at 900°C, the Si NDs have a mean diameter of 3 nm and a sheet density of 10¹¹/cm², as determined by the transmission electron microscopy. The photoluminescence (PL) spectrum is red-shifted after the annealing. The electroluminescence spectrum from Al/Si NDs embedded silicon nitride/ Si device structure was investigated. The spectrum was spread from 400 to 750 nm and is blue-shifted as compared to the PL spectrum. The device electrical characteristics, with as-deposited and annealed Si NDs embedded in the silicon nitride layer, were investigated at room temperature. The current transport was found to be strongly correlated to the Si NDs. The annealed Si NDs have lower energy states, which are consistent with the shift of the PL spectrum.     

Thermoelectric Properties of Triple-Filled BaxYbyInzCo4Sb12 Skutterudites

Indium-filled skutterudites are promising power generation thermoelectric materials due to the presence of an InSb nanostructure that lowers the thermal conductivity. In this work, we have investigated thermoelectric properties of triple-filled Ba _x Yb _y In _z Co₄Sb₁₂ (0 ≤ x, y, z ≤ 0.14 actual) compounds by measuring their Seebeck coefficient, electrical conductivity, thermal conductivity, and Hall coefficient. All samples were prepared by a melting–annealing–spark plasma sintering method, and their structure was characterized by x-ray diffraction and transmission electron microscopy (TEM). TEM results show the development of an InSb nanostructure with a grain size of 30 nm to 500 nm. The nanostructure is present in all samples containing In and is also detected by specific heat measurements. The Seebeck and Hall coefficients indicate that the compounds are n-type semiconductors. Electrical conductivity increases with increasing Ba content. Thermal conductivity is strongly suppressed upon the presence of In in the skutterudite structure, likely due to enhanced boundary scattering of phonons on the nanometer-scale InSb inclusions. The highest thermoelectric figure of merit is achieved with Ba_0.09Yb_0.07In_0.06Co₄Sb_11.97, reaching ZT = 1.25 at 800 K.