DESIGN OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE

ABSTRACT

Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.     

The Ferroelectric Memory and its Applications

The ferroelectric memory is not only an ideal memory with clear advantages such as non-volatility, low power consumption, high endurance and high speed writing, but is also the most suitable device for memory embedded applications. Its manufacturing process makes it more compatible with the standard CMOS process than the traditional non-volatile memory process, since it does not require high voltage operation, and the ferroelectric process does not influence the characteristics of the CMOS devices used in logic cells, analog cells and core cells. In the spreading of Intellectual Property (IP) application for the LSI Industry, this embedded application takes on a more important role. In the near future, the ferroelectric memory technology will be taken into reconfigurable devices as programmable interconnect switches besides being used as embedded memories. These ferroelectric memory based reconfigurable devices can be used as Dynamic Programmable Gate Array (DPGA), which are able to be reconfigured from their original logic in a system under an operation mode. New logic circuits will operated with lower power consumption or a resume function by introducing ferroelectric gated transistors or ferroelectric capacitors. Even though ferroelectric memory technology has many advantages, it is not popular yet, since, the conventional semiconductor process degrades the ferroelectric layer easily. The means to prevent degradation of ferroelectric films in the silicon wafer process will also be discussed.     

PROPERTIES OF FERROELECTRIC P(VDF-TrFE) 70/30 COPOLYMER FILMS AS A GATE DIELECTRIC

ABSTRACT

We directly formed the organic ferroelectric P(VDF-TrFE) 70/30 copolymer film by the spin coating for making the MFS structure in the silicon wafer. To understand the crystallization behavior of P(VDF-TrFE) 70/30 copolymer, the morphologies of copolymer thin films were studied by AFM and XRD. AFM studies revealed that as grown and annealed films showed surface roughness greater than amorphous films due to crystallization. The XRD spectrum of the films subjected to various annealing temperatures showed β -phase and this phase content was maximum at 140°C annealing. The capacitance shows hysteresis behavior like a buttery shape due to the polarization reversal in the film and this result indicates clearly that the film has a ferroelectric property. The dielectric constants of the P(VF₂-TrFE) copolymer films calculated from the capacitance at the two peak points of the C-V characteristics were about 8.7.     

Domains in ferroelectric VDF/TrFE copolymer thin films: Investigated by a new optical probe method

Abstract

A new optical probe method was developed by using electro-optic and piezoelectric effects and a phase sensitive detection to determine the polarization of domains in ferroelectric thin films. Ferroelectric domains within a region smaller than 1 μm were detected in annealed VDF(65)/TrFE(35) copolymer thin films. The switching dynamics of these individual domains were also investigated by using this method.     

Study on property variation due to the interface between PZT and electrode

Abstract

The ferroelectric capacitors are fabricated using RuO₂/Pt electrode to examine the electrode effect on ferroelectric properties. PZT films are prepared by metalorganic decomposition (MOD) on sputter deposited electrodes. In particular, inductively coupled plasma(ICP) etcher is used to minimize the etching damage. In addition, TiO₂ reaction barrier layer is also employed to retard the degradation of ferroelectric properties due to the reaction between a passivation layer and PZT film. The better hysteretic properties were obtained from Pt/RuO₂/PZT/RuO₂/Pt ferroelectric capacitors. The enhancement of ferroelectric properties is likely attributed to the modification in the microstructure of PZT film. The interfacial modification would be affected by the factors such as surface roughness, stress, and porosity of RuO₂ film. The result implies RuO₂/Pt would be a good electrode for a nonvolatile memory application.     

The Effects of Integration Processes on Properties of One Transistor MFMPOS Memory Devices

Integration processing of one-transistor memory devices deals with the following issues: film quality of ferroelectric materials, integration process induced damages such as etching and forming gas annealing damage of ferroelectric materials, the alignment for devices. In order to make high quality one-transistor memory devices, integration processes including nitride gate replacement, oxide trench etching structures, selective deposition, etc. have been investigated for fabrication of one transistor MFMPOS (M: Metal, F: Ferroelectrics, M: Metal, P: polysilicon, O: oxide, S: silicon) memory devices. The integration processes for one transistor memory device have also been optimized to reduce process-induced damages. Based on the experimental results, MOCVD selective deposition can make higher quality patterned ferroelectric thin films, damascene structure with CMP processes can reduce the etching damages. Therefore, the high quality one transistor MFMPOS memory devices have been made.     

Current status of resistive nonvolatile memories

Several emerging nonvolatile memories (NVMs) such as ferroelectric memory, magnetoresistive rams and ovonic universal memory are being developed for possible applications. Resistive random access memory (RRAM) is another interesting competitor in the class of NVMs. The RRAM is based on a large change in electrical resistance when the memory film is exposed to voltage or current pulses, and can keep high or low resistance states without any power. The ideal RRAM should have the superior properties of reversible switching, long retention time, multilevel switching, simple structure, small size, and low operating voltage. Perovskite oxides, transition metal oxides, and molecular materials were found to have resistive memory properties. This presentation reviews the ongoing research and development activities on future resistance NVMs technologies incorporating these new memory materials. The possible basic mechanisms for their bistable resistance switching are described. The effect of processing, composition, and structure on the properties of resistive memory materials and consequently the devices are discussed.     

Monolayer-Mediated Patterning of Integrated Electroceramics

Integrated electroceramic thin-film devices on semiconducting or insulating substrate materials offer a wide variety of attractive attributes, including high capacitance density, nonvolatile memory, sensor/actuator ability, and other unique electrical, electromechanical, magnetic and optical functions. Thus the ability to pattern such electroceramic thin films is a critical technology for future device realization. Patterned oxide thin-film devices are typically formed by uniform film deposition followed by somewhat complicated post-deposition ion-beam or chemical etching in a controlled environment i.e., a subtractive method. We review here an upset technology, a different way of patterning, by an additive approach, which allows for the selective deposition of electroceramic thin layers without such post-deposition etching. In this method, substrate surfaces are selectively functionalized with hydrophobic self-assembled monolayers to modify the adhesion of subsequently deposited solution-derived electroceramics. The selective functionalization is achieved through microcontact printing (-CP) of self-assembled monolayers of the chemical octadecyltrichlorosilane on substrates of current technical interest. Subsequent sol-gel deposition of ceramic oxides on these functionalized substrates, followed by lift-off from the monolayer, yields high quality, patterned oxide thin layers only on the unfunctionalized regions. A variety of micron-scale dielectric oxide devices have been fabricated by this method, with lateral resolution as fine as 0.5 m. In this paper, we review the monolayer patterning and electrical behavior of several patterned electroceramic thin films, including Pb(Zr,Ti)O₃ [PZT], LiNbO₃, and Ta₂O₅. A multilevel example is also given which combines selective MOCVD deposition of metal electrodes and sol-gel patterned PZT for Pt//PZT//Pt//Si(100) ferroelectric memory cells.     

MFIS and MFMIS structures using Pb(Zr,Ti)O3 films for nonvolatile memory devices

Abstract

In this work, metal / ferroelectric / insulator / semiconductor (MFIS) and metal / ferroelectric / metal / insulator / semiconductor (MFMIS) structures using Pb(Zr, Ti)O₃ (PZT) films were fabricated and characterized for nonvolatile NDRO memory device. 300nm-thick PZT films were deposited by reactive RF magnetron sputtering method on ZrTiO₄(ZT)/Si and Pt/ZT/Si substrates. C-V hysteresis were measured in both MFIS and MFMIS structures. By using a small-size MFM capacitor on a large-size MIS structure, it was found that the memory window of MFMIS structure was larger than that of the MFIS structure. There is a critical area ratio (S_MIS/S_MFM) in MFMIS structure. When an area ratio in MFMIS structure is below 12, the memory window increased with increasing area ratio. We could obtain that the memory window of MFMIS structure with a S_MIS/S_MFM of 11.8 was 2.1 V and 3.2 V with an applied voltage at 3 V and 5 V.     

Pt/TiN electrodes for stacked memory with polysilicon plug utilizing PZT films

Abstract

The mechanism of TiN barrier metal oxidation of Pt/TiN electrodes are investigated for planarized stacked memory utilizing lead zirconate titanate (PZT). Thinner (<100 nm) and highly oriented platinum films are required in gigabit scale ferroelectric nonvolatile memories whose capacitor size is comparable to PZT grain size. Oxygen diffusivity to oxidize TiN is found to depend on the Pt film thickness. In cross-sectional TEM images of PZT/Pt/TiN/Si, titanium oxide is observed beneath the Pt grain boundary. The oxygen is diffused through the Pt grain boundary under heat treatment in an oxygen atmosphere for crystallization of PZT films, and oxidizes the underlying TiN barrier metal.     

继电保护装置存储异常变位的容错设计与应用

继电保护装置用到的存储器类型包括非易失性存储器和随机存取存储器2种。这2种存储器的异常变位(单粒子效应)将导致继电保护装置的关键数据丢失、程序运行异常、整机功能失效和误动。文中针对随机存取存储器异常变位,设计了实时内存变位监控及变位恢复机制,避免了异常变位造成继电保护装置功能失效的问题;针对非易失性存储器异常变位,设计了冗余加固的文件存储方法,消除了异常变位对继电保护装置的影响。文中所提设计方法通过中子散列试验得到了实际验证,已应用于超高压继电保护装置并挂网运行,方案切实有效。     

Electric Properties of Pt/PbZr 0.53 Ti 0.47 O 3 /LaAlO 3 /Si Structure

Pb(Zr,Ti)O 3 (PZT) is a well known ferroelectric material for nonvolatile memory applications. However, interfacial diffusion and reaction are the main issues when PZT films were deposited directly on silicon. One way to overcome this obstacle is to deposit a barrier layer between PZT and Si. In this work, Pt/PbZr 0.53 Ti 0.47 O 3 /LaAlO 3 /Si structure has been fabricated to study the electric properties. PbZr 0.53 Ti 0.47 O 3 films with 300 nm thickness and LaAlO 3 buffer layers with 30 nm thickness were prepared by pulsed laser deposition technique on n-type Si (100) substrates at 650 C and 450 C, respectively. X-ray diffraction shows that polycrystalline PbZr 0.53 Ti 0.47 O 3 film was formed on amorphous LaAlO 3 buffer layer. The Auger electron spectrometer demonstrates that LaAlO 3 buffer layer effectively prevent Si and Ti, Pb interdiffusion between PZT and Si substrates. For the Pt/PbZr 0.53 Ti 0.47 O 3 /LaAlO 3 /Si structure, the current density-voltage measurement showed a typical leakage current density of about 10 m 7 A/cm 2 at 8 V applied voltage. Furthermore, it has been measured that the Pt/PbZr 0.53 Ti 0.47 O 3 /LaAlO 3 /Si heterostructures exhibit ferroelectric switching properties, showing a memory window as large as 2 V under a ramp rate of 200 mV/s at 1 MHz.     

Sensor and optical properties of ferroelectric and porous fluoropolymers

The fabrication and performance of sensors utilizing the piezoelectric properties of P(VDF/TrFE) copolymer thin films are described. The IR spectra of porous PTFE films, and electron micrographs showing their structure, are presented. Finally the fabrication and performance of a sensor utilizing the piezoelectric properties of a porous PTFE film in contact with a compact or normal PTFE film are described.     

UHV processing of ferroelectric barium magnesium fluoride films and devices

Barium magnesium fluoride (BaMgF4) has recently emerged as a strong candidate for application as the gate dielectric in ferroelectric random access memory (FERRAM) devices with nondestructive readout (NDRO). In earlier papers we reported the successful growth of oriented BaMgF4 films on Si(100) and other substrates in a ultrahigh vacuum (UHV) system, as well as the results of the structural and electrical characterization of these ferroelectric films. In the present paper, we review some of the earlier results, and also examine the effect of variations in the growth temperature and various post-growth anneals on the stoichiometry, crystallinity, orientation, and electrical characteristics of the BaMgF4 films. Initial attempts at integrating the ferroelectric field-effect transistor (FEMFET) with the standard CMOS VLSIC processing, as well as the effect of adding a thin capping layer of SiO2 on the BaMgF4 will also be described.     

Ferroelectric nonvolatile logic

Abstract

This paper describes the design of nonvolatile logic elements using ferroelectric materials. Two separate approaches are discussed. The first approach involves shadowing a CMOS latch or flip-flop with a single bit 2T/2C ferroelectric memory. The second approach offers improved density by integrating ferroelectric capacitors within the logic element. Both designs employ non-switching ferroelectric capacitors to establish the optimum bit line load in the absence of sufficient parasitic capacitance. The paper further describes low-voltage and wide-voltage design techniques used to realize 2.7 – 5.5V products on a “5-volt” ferroelectric process. These same techniques allow 1.8V ferroelectric memory products to be designed using the upcoming generation of production ready “3-volt” ferroelectric materials. Layout effects are discussed, as well as bit/cell ratio optimization.     

High temperature processing of ferroelectric thin films using interconnect wafer technology

Abstract

There is interest in ferroelectric thin films for uncooled IR detector applications. Currently the processing of these devices takes a fully integrated approach where the thin films are deposited directly onto underlying CMOS readout circuitry, thereby imposing severe limits on the thermal budget available for the crystallisation of the ferroelectric material. This is incommensurate with obtaining the best ferroelectric properties from materials such as lead scandium tantalate (PST) which requires elevated temperature processing to attain the highest merit figures for IR detection. In this paper thin film PST processed within the CMOS survivability envelope will be compared to that processed at temperatures up to 850°C. A novel interconnect wafer technology will be outlined which enables processing to be extended to such temperatures. It will be shown that elevated temperature processing of the PST film can result in dramatic improvement of the materials merit figure for IR detection     

Reliability properties of low-voltage ferroelectric capacitors and memory arrays

We report on the reliability properties of ferroelectric capacitors and memory arrays embedded in a 130-nm CMOS logic process with 5LM Cu/FSG. Low voltage (<1.5 V) operation is enabled by the 70-nm thick MOCVD PZT ferroelectric films. Data loss resulting from high temperature bakes is primarily caused by the imprint effect, which shows /spl sim/1.5 eV time-to-fail activation energy. Excellent bit endurance properties are observed on fully packaged memory arrays, with no degradation up to 10/sup 13/ write/read polarization switching cycles. Retention measured after 10/sup 12/ switching cycles demonstrates no degradation relative to arrays with minimal cycling.     

Growth and characterization of epitaxial SrBi2Ta2O9 films on (110) SrTiO3 substrates

Abstract

SrBi₂Ta₂O₉ (SBT) is an attractive material for nonvolatile ferroelectric memory applications. In this paper we report on the deposition of highly epitaxial and smooth SrBi₂Ta₂O₉ films on (110) SrTiO₃substrates. The films were grown by pulsed laser deposition at temperatures ranging from 600 to 800°C and at various laser fluences from a Bi-excess SBT target. The background oxygen pressure was maintained at 28 Pa during the film deposition. Structural characterization of the films was performed by x-ray diffraction. Atomic force microscopy was used to investigate morphology and growth of the films. The films grew with preferred (115) or (116) orientation. The roughness was of the order of unit cell height. The films display a growth pattern resulting in corrugated film morphology.     

Agile microwave devices

After years of material optimization and laboratory demonstrations of devices, the application of ferroelectrics in microwave technology is gaining momentum. At present, ferroelectric films are used in passive and agile microwave devices and systems including: · parallel-plate and coplanar-plate varactors · tunable resonators, filters, and matching networks · phase shifters and delay lines · ferroelectric-based frequency converters and harmonic generators · voltage-controlled oscillators (VCOs) and amplifiers using ferroelectric varactors · steerable beam antennas and phased arrays · tunable, frequency selective, and impedance surfaces · tunable thin-film bulk acoustic wave resonators (TFBARs) and filters · high-density decoupling capacitors and field dielectrics in CMOS devices. The current status of agile microwave technology is partly summarized in a book chapter [1] and a book [2]. The latter also gives a detailed review of applications of ferroelectrics in microwave technology and a forecast of possible future developments in the field. Several companies have started commercial development and marketing of ferroelectric varactors and devices based on them [3]-[6]. This article highlights the advantages of ferroelectric varactors and gives a few examples of devices and system-level commercialization strategies.     

BaMgF4 thin film development and processing for ferroelectric FETS

Abstract

A ferroelectric memory field-effect transistor (FEMFET) where a ferroelectric thin film is incorporated directly into the gate structure of the transistor is attractive, because it provides not only nonvolatility, but also nondestructive readout (NDRO). At Westinghouse, we are currently developing a FEMFET using thin film barium magnesium fluoride (BaMgF₄), a ferroelectric material that was discovered in 1969, but was not fabricated in thin film form until 1989. The BaMgF₄ films are grown by evaporation in an ultrahigh vacuum (UHV) chamber on clean Si(100). The natural tendency of these films to grow with the ferroelectric a-axis in the Si(100) plane has been overcome to obtain more random orientation with larger reversible polarization perpendicular to the film. A capping layer (SiO₂) has been found to be essential for process integrability of these BaMgF₄ films. Ti-W metallization produced only a slight reduction in the capacitance-voltage (C-V) memory window. Switching speed of these films has been measured to be 40 to 45 nanoseconds. The first FEMFET fabricated with BaMgF₄ has exhibited 18 Volt memory hysteresis window with better than 10⁵ on/off current ratio for 20 Volt programming.