Robust hybrid pitch detector

A hybrid pitch detector characterised by parallel analysis of the speech signal in temporal, spectral and cepstral domains is proposed. The voiced/unvoiced decision and pitch period evaluation is realised by a logical analysis of the results from three domains. The experimental analysis shows the robustness of the detector for noisy and telephone speech.<>     

A programmable NMOS DRAM controller for microcomputer systems with dual-port memory and error checking and correction

An NMOS DRAM controller for use in microcomputer systems based on the iAPX-86 and iAPX-286 microprocessor families or on the Multibus system bus is described. The controller provides complete support for dual-port memories and memories with error checking and correction. The controller has programmable attributes for configuring it to the particular requirements of the system. The controller uses parallel arbitration to minimize arbitration delay. A memory cycle will start on the same clock edge that samples a command if the cycle has been previously enabled. Novel logic and circuit design techniques have been used to achieve 16 MHz operation, 20 ns input setup time, and 35 ns output delay time.     

基于纠错算术码的信源信道自适应联合编解码系统

对信源信道自适应联合编码方法进行了研究,提出了一种新的基于纠错算术码的联合信源信道编解码系统。该系统在编码端利用算术码内嵌禁用符号实现信源信道一体式编码,即利用马尔科夫信源模型和根据信道状态信息自适应地调整禁用符号概率大小从而调整编码码率来实现信道自适应;在解码端,推导出了基于MAP的解码测度数学公式并基于此测度公式提出了一种改进的堆栈序列估计算法。与传统的信道自适应编码算法不同,该自适应编码算法只需调整一个参数:禁用符号,且理论上可获得连续可变的编码码率。实验结果表明,与经典的Grangetto联合编码系统以及分离编码系统相比,所提出的编码系统具有明显改善的性能增益。     

Probabilistic crisscross error correction

The crisscross error model in data arrays is considered, where the corrupted symbols are confined to a prescribed number of rows or columns (or both). Under the additional assumption that the corrupted entries are uniformly distributed over the channel alphabet, and by allowing a small decoding error probability, a coding scheme is presented where the redundancy can get close to one half the redundancy required in minimum-distance decoding of crisscross errors     

Signal-blocking-based adaptive beamformer with simple direction error correction

A novel beamformer is proposed, based on the Duvall beamforming structure. The Duvall beamformer, which blocks the desired signal by using its direction information, suffers from performance degradation due to errors in the information. The proposed beamformer is very insensitive to such errors by employing a simple direction estimation, which is well suited to the Duvall structure.     

具有校正功能的液面检测器设计与应用

为了以更低的成本和更加简单的操作方式来实现液面计量,提出了一种新的具有校正功能的液面检测器,其输出信号是脉冲流。通过设计具有比较电路和校验电路的芯片,该液面检测器只需要简单地调整参数就可以实现各种液位传感器的修正,然后使用配置范围在3.97到123.34毫米之间的液位传感器,相应的输出频率范围可以达到3.12至57.25 kHz。最后进行了实际雨量测量实验,经过校正后,测量的最大频率误差为1.46%,验证了提出的液面检测器的正确性和精确性。     

Adaptive algorithms with nonlinear data and error functions

The tools of nonlinear system theory are used to examine several common nonlinear variants of the LMS algorithm and derive a persistence of excitation criterion for local exponential stability. The condition is tight when the inputs are periodic, and a generic counterexample is demonstrated which gives (local) instability for a large class of such nonlinear versions of LMS, specifically, those which utilize a nonlinear data function. The presence of a nonlinear error function is found to be relatively benign in that it does not affect the stability of the error system. Rather, it defines the cost function the algorithm tends to minimize. Specific examples include the dead zone modification, the cubed data nonlinearity, the cubed error nonlinearity, the signed regressor algorithm, and a single-layer version of the backpropagation algorithm     

Incremental digital position encoder with error detection and correction

A digital position encoder is described which combines features of absolute and incremental encoders. A track encoded with a pseudorandom sequence provides absolute position information for an incremental encoder, allowing the detection and correction of errors, while requiring only two code tracks and four read heads.<>     

High-speed ΔΣ ADC with error correction

A digital error correction scheme is described for ΔΣ ADCs with multibit quantisers. It operates in the background and remains effective even for very low oversampling ratios     

A 12-bit successive-approximation-type ADC with digital error correction

A correction algorithm has been implemented that gives an almost twofold improvement in conversion speed without loss of accuracy or changes to the analog circuitry of a slower design. The design of a smart successive-approximation register chip, which has been fabricated in a double poly CMOS process and takes up 18 mil/SUP 2/ in die area, is described. The area is 13% larger than that of an A/D converter utilizing the same analog chip but a conventional digital chip without error correction. A speed improvement from 12 to 7 /spl mu/s was obtained with digital error correction.     

多点标定的自适应非均匀性校正方法

为了实现对红外焦平面阵列(IRFPA)获取图像的实时高精度非均匀校正,提出了一种基于多点标定的自适应非均匀性校正算法,该算法假定在环境温度变化时,校正后输出图像数据的差值与已标定的数据存在线性关系,对其进行分块并配对,采用最小二乘法,以平方和最小为准则,自适应修正校正系数,以达到实时调整非均匀校正的校正系数,对环境温度变化引起的非均匀性进行补偿的目的.实验结果表明,该方法既提高了非均匀性校正的精度又能满足实时性要求,可广泛应用于光电火控、红外成像制导等对实时性和成像质量均有较高要求的应用场合.     

A frequency error resistant blind CDMA detector

This paper presents an enhanced version of the previously proposed blind anchored interference-mitigating detector (BAID) for code-division multiple-access transmission. Such a detector, named extended complex BAID (EC-BAID), features invariance to a phase error on the useful channel's carrier and reveals resistance to a large frequency shift (e.g., Doppler shift) on interfering carriers. The EC-BAID is also shown to bear a sensitivity to residual carrier frequency errors on the desired channel which is lower by three orders of magnitude with respect to the case of a data-aided minimum mean-square-error receiver. The performance of the EC-BAID is computed theoretically, and is validated by computer simulations under a variety of system configurations     

Logic design error diagnosis and correction

Logic verification tools are often used to verify a gate-level implementation of a digital system in terms of its functional specification. If the implementation is found not to be functionally equivalent to the specification, it is important to correct the implementation automatically. This paper describes a formal method for the diagnosis and correction of logic design errors in an incorrect gate-level implementation. We use Boolean equation techniques to search for potential error locations. An efficient search and pruning algorithm is developed by introducing the notion of immediate dominator set. Two correction procedures are proposed. Gate correction corrects errors such as wrong gate type, missing inverters, etc.; line correction corrects errors such as missing wires and wrong connections. Our method is robust and covers all, simple design errors described by Abadir et al. (1988). Experimental results for a set of ISCAS and MCNC benchmark circuits demonstrate the effectiveness of the proposed techniques     

前向纠错技术在EPON中的应用研究

在EPON中引入前向纠错(FEC)技术,能有效地增加PON的光分路数和增大信号的传输距离。对于在EPON中加入FEC功能所涉及到的FEC线路综合编码、帧结构的设计以及兼容性等问题进行了分析,并进一步给出了相应的解决方案。     

非均匀性校正的长波光导探测器读出电路设计

在航天遥感领域,波长在10m以上的长波探测器仍以HgCdTe光导型探测器为主,在红外探测成像方面发挥着重要作用。非均匀性是目前长波光导探测器突出的问题之一,设计了一种数模混合的非均匀性校正的长波光导探测器读出电路。该电路不仅可以有效地解决线列长波光导探测器电阻非均匀性问题,还可以增大ROIC输出信号的动态范围,几乎不增加读出电路功耗。经过仿真测试表明:非均匀性问题有了明显的改善,能够使其非均匀性降为0.5%以内,在常温和低温下都能正常工作。该校正电路不仅能解决当前工程中的关键问题,还对今后高性能大面阵长波光导探测器读出电路的设计具有重要的指导意义。     

基于FPGA的前向纠错算法

研究数字音频无线传输中的前向纠错(FEC)算法的设计及实现,对前向纠错中的主要功能模块,如RS编解码、交织器与解交织器等给出基本算法及基于现场可编程门阵列(FPGA)和硬件描述语言的解决方案.选用硬件描述语言VerilogHDL,在开发工具QuartusⅡ4.2中完成软核的综合、布局布线和汇编,在Modelsim中进行时序仿真验证,最终下载到开发板中进行电路验证及测试.     

Built-in testable error detection and correction

A method for design of built-in testable (BIT) error detection and correction (EDAC) circuits is presented that uses up to 65% less test hardware than customary BIT implementations. A 1-μm CMOS, 16-bit EDAC designed and fabricated with this technique exhibits >99% fault coverage in 10 μs at 25 MHz. Built-in test impacts the speed performance by only one gate delay regardless of the size of the EDAC. Various faults are injected into the chip to verify the effectiveness of built-in test     

Sparse-graph codes for quantum error correction

Sparse-graph codes appropriate for use in quantum error-correction are presented. Quantum error-correcting codes based on sparse graphs are of interest for three reasons. First, the best codes currently known for classical channels are based on sparse graphs. Second, sparse-graph codes keep the number of quantum interactions associated with the quantum error-correction process small: a constant number per quantum bit, independent of the block length. Third, sparse-graph codes often offer great flexibility with respect to block length and rate. We believe some of the codes we present are unsurpassed by previously published quantum error-correcting codes.