基于交叉开关结构的片上光互连网络研究

最近一些研究小组提出光片上网络以解决现有电片上网络无法满足未来片上系统(SoC)高带宽、高能效要求的问题。光交叉开关作为光互连中必不可少的一部分,既可以用于光路由器的设计中,又可以用来构建一个全互连的网络。文章综述了交叉开关的发展,并对现阶段提出的光交叉开关结构在能耗与通信过程方面进行了分析、对比。最后结合实例研究了光交叉开关在光片上网络中的应用,结果表明光交叉开关在光互连中具有很好的应用前景。     

基于多端口存储器互连结构的多处理器系统芯片设计

多处理器系统芯片设计的关键问题之一是微处理器之间的互连结构.在总线互连结构和开关互连结构之后,提出了基于多端口存储器的第3种互连结构.利用VHDL进行了多时钟多端口存储器设计,并利用EDA工具进行了片上系统芯片的多微处理器数据通讯的功能仿真.分析了基于总线、基于开关、基于多端口存储器的3种互连结构的特点.研究表明基于多端口存储器的互连结构具有异步数据传输,数据缓冲功能;具有数据传输延时小,多微处理器系统芯片的拓扑阵列规模可扩展的优点.     

基于PCIE总线的多DSP系统接口设计和驱动开发

开发了多DSP雷达信号处理板卡。对DSP互连、DSP与FPGA通信以及基于Xilinx FPGA的PCIE总线进行设计。系统可扩展性好、效率高。用DriverStudio开发了WDM总线驱动程序,具有很好的通用性和可移植性。     

一种双模式的CMOS现场可编程模拟阵列的分析与设计

本篇文章提出了基于采用高度灵活的互连盒的互连网络的一种新型的现场可编程模拟阵列(FPAA)结构,该结构可以在双模式下工作包括离散时间模式和连续时间模式,以追求在不同应用场合下的性能要求。高度灵活的互连盒中的开关不仅用来作为可编程开关还直接作为开关电容中电荷转移的开关来使用,大大减少了离散时间模式下信号路径上的开关,提高了整体电路的性能。该款FPAA采用0.18um CMOS工艺,3.3V电源电压。后仿结果显示互连网络的最大带宽可达265MHz, 从示例的测试结果可以看出该款FPAA在连续时间模式下可工作在2MHz信号带宽下,无杂散动态范围可达54dB, 离散时间工作模式下的处理精度可达96.4%。     

多DSP并行处理器的设计与实现

采用ADI公司的4片ADSPTS201作为主处理芯片,以LINK口互连的松耦合结构和Clust总线互连的紧耦合结构作为多DSP的拓扑互连形式,设计并研制了基于PCI的高速并行信号处理器。该处理器在设计上采用CadenceSPB15.5做了充分的信号仿真,保证了系统的信号完整性,经测试系统运行稳定。同时,该信号处理器具备松耦合和紧耦合2种互连方式,可满足更多种形式的算法结构,在图像处理、实时信号处理能方面有较好的应用价值。     

相干激光测风雷达信号处理系统研究

介绍了基于相干探测方式的多普勒激光测风雷达的基本组成结构和原理,着重对激光测风雷达的信号处理系统进行了研究.文中给出了信号处理系统中所采用的多普勒信号处理方法,对采集到的多普勒回波信号进行了仿真研究.采用商业数据采集卡和LABVIEW软件,设计了相干激光测风雷达信号处理系统,并通过搭建的平台实现了激光视向风速的测量.通过模拟的多普勒回波信号,对信号处理系统进行了测试验证,实验结果证明了该信号处理系统能够达到0.8 m/s的速度测量精度.     

IEEE 1149.4标准实验测试结构设计和扩展研究

本文采用复杂可编程逻辑器件（CPLD）和分立器件,设计实现了IEEE 1149.4混合信号边界扫描标准实验测试结构。为了提高互连测试的故障诊断能力,文中对模拟边界模块（ABM）开关结构进行了一些修改。针对ABM单元的这些修改允许测试者可以将模拟输入信号与多个电压进行比较。当测试者在简单互连或扩展互连中遇到桥接故障,扩展的ABM开关结构使得故障更容易探测。     

一种云服务器互连芯片交叉开关的设计与实现

在高端云服务器系统中,计算节点间的互连芯片通过Cache一致性协议将多计算节点互连组成分布式和共享内存空间系统,对接口传输速率和路由交换效率要求较高。文中通过分析Cache一致性协议报文的传输特点和互连网络转发需求,设计实现了一种互连芯片的高阶非对称交叉开关。设计通过了系统级的仿真验证,基于FPGA实现的云服务器互连芯片原型验证系统进行了实际带宽测试和芯片带宽匹配优化。互连芯片流片后的系统实测结果表明,满足功能要求,互连网络处理模块延迟8. 75ns,吞吐率65. 03%,达到了设计目标。     

基于高速串行总线的可重构信号处理机

介绍了一种基于高速串行总线的机载火控雷达可重构信号处理机的设计与实现,以及高速串行总线的技术优势,分析了机载火控雷达可重构并行信号处理机系统互连的需求,讨论了处理机的系统架构、串行总线协议、串行总线端点和链路管理器的设计实现和总线错误监测及处理方法。该处理机不仅有效解决了数据传输的瓶颈问题,而且实现了数据传输拓扑结构的可重构,提高了信号处理系统的灵活性和可靠性。     

基于光纤模式数据采集方案的阵列快拍成像雷达

阵列快拍成像雷达采用阵列天线雷达成像体制,通过高速微波开关切换和高速数据采集,可以同时实现对目标的空间分辨和时间分辨,即实现雷达快拍成像,该技术在飞行器平台的辅助导航、交通监测等领域具有广阔的应用前景。阵列快拍成像雷达的特点是能够快速成像,核心技术包括微波信号收发、高速数据采集与传输、实时成像处理及阵列天线高速微波开关切换。其中,高速数据采集与传输是实现快速成像是正确成像的关键,数据缺失会导致图像散焦。本文首先分析了阵列快拍成像雷达成像原理及信号采样对数据采集与传输系统的要求;继而提出了基于光纤传输模式的数据采集与传输系统方案,系统采用四路高速AD对雷达基带信号进行采样,在FPGA中进行复数运算,通过光纤通道传送到主控计算机,系统传输速率可以达到2.5Gbps;最后,通过阵列快拍成像实验验证了系统的性能。      

Resource allocation for statistical quality of service provision in buffered crossbar switches

The buffered crossbar switch is a promising switching architecture that plays a crucial role for providing quality of service (QoS) in computer networks. Sufficient amount of resources—bandwidth and buffer space—must be allocated in buffered crossbar switches for QoS provision. Resource allocation based on deterministic QoS objectives might be too conservative in practical network operations. To improve resource utilization in buffered crossbar switches, we study the problem of resource allocation for statistical QoS provision in this paper. First, we develop a model and techniques for analyzing the probabilistic delay performance of buffered crossbar switches, which is described by the delay upper bound with a prescribed violation probability. Then, we determine the required amounts of bandwidth and buffer space to achieve the probabilistic delay objectives for different traffic classes in buffered crossbar switches. In our analysis, we apply the effective arrival envelope to specify traffic load in a statistical manner and characterize switch service capacity by using the service curve technique. Instead of just focusing on one specific type of scheduler, the model and techniques developed in this paper are very flexible and can be used for analyzing buffered crossbar switches with a wide variety of scheduling algorithms. Copyright © 2007 John Wiley & Sons, Ltd.     

A Novel Integrated Multistage 2-D MEMS Optical Switch With Spanke–Benes Architecture

Due to the emergence of high-capacity wavelength-division multiplexing transmission systems, new optical cross-connect (OXC) architectures that make a large number of fiber/wavelength counts to switch the signal in the optical domain are needed. Optical microelectromechanical system (MEMS) switches are regarded as the most promising optical switch technology to achieve such functionalities. In this paper, we propose a novel integrated multistage two-dimensional (2-D) MEMS optical switch design with Spanke-Benes architecture and compare it with the conventional crossbar architecture, the L-switching architecture, and Shuffle-Benes architecture. Our proposed architecture is very suitable for building large-port-count 2-D MEMS switches and achieves much better performance in terms of beam divergence loss, longest optical path, mirror radius, substrate size, port-to-port repeatability, and power consumption than the other three architectures. Furthermore, compared with the 2-D conventional crossbar switch commercially available now, the proposed architecture can save 50% mirrors, shorten 87.5% longest optical path, minify 65% mirror radius, and shrink 90% substrate size.     

Where buses cannot go

No aspect of computer design is sacred, not even the system bus, which is giving way to switches in multiprocessing systems, where performance is key. System buses, which string computers together out of circuit boards, have come to strangle system performance in many cases. Another interconnection architecture, though, can free a system from the bus's clutch. Variously known as a switch, crossbar, or crosspoint, it has long been used in speciality computers and is now making its way into lower-cost machines. Meanwhile, silicon and packaging technology have been refined to the point that the crossbar architecture can vie with the system bus for a place in low-cost multiprocessors. More specifically, the crossbar is well suited to use in distributed memory systems, where there is a need for broad path ways for communications between the chunks of memory themselves. The roots of such an approach go deep. In fact, it may be said to have started with an idea for keeping as much data traffic as possible out of general circulation: cache memory     

Exact and approximate analytical modeling of an FLBM-based all-optical packet switch

This paper develops both exact and approximate models for the analysis of an all-optical packet switch based on a fiber-loop buffer memory (FLBM). The switch structure and operation is based on the fully shared buffer architecture of the Research and Development in Advanced Communications in Europe - ATM Optical Switching (RACE-ATMOS) project , which uses individual wavelengths to store fixed-length packets in the fiber-loop buffer. An exact model of the switch has been developed , which can be used to determine the blocking performance of the switch and obtain both its throughput and packet loss characteristics. It has been used to study the switch performance under different loading conditions and for different values of the key design parameters of the switch. This model is difficult to use for studying large switches of this kind because of computational complexities. To tackle this problem, an approximate queuing model has also been presented, which may be used to study the performance of large switches of this kind. The results obtained by the two methods are compared to confirm that the approximate model works well under typical loading conditions of the switch.     

Two-module stage optical switch network

A large-scale optical switch array based on guided-wave technology using two-module-stage network architecture is proposed. Networks are derived from a generalized three-stage switch network. Two types of architecture are demonstrated. In the first, building blocks in each module are 1×n, n×m nonblocking switches or n×r switch that can route limited numbers of input signal. In the second, crossbar, Banyan, or four-stage wide-sense nonblocking network is used as building blocks. The interconnection is simpler than for the first type. Network architectures that use Banyan or wide-sense nonblocking network building blocks are classed as thinned-out Banyan networks     

电子战仿真中信号处理系统的软件化设计

在半实物电子战仿真系统中,要求雷达信号处理系统完成多种雷达体制的模拟,传统的基于任务、面向硬件的实现方法不能满足多种雷达工作方式的要求。随着数字化技术和软硬件的不断发展,雷达软件化设计成为雷达信号处理的发展方向。本系统采用雷达软件化的设计方法,从硬件平台和软件结构介绍了系统的实现。该系统可在不同的雷达工作模式间进行切换,充分体现了灵活性、可扩展性和兼容性等特点。     

A New Architecture for Nonblocking Optical Switching Networks

With the current technology, all-optical networks require nonblocking switch architectures for building optical cross-connects. The crossbar switch has been widely used for building an optical cross-connect due to its simple routing algorithm and short path setup time. It is known that the crossbar suffers from huge signal loss and crosstalk. The Clos network uses a crossbar as building block and reduces switch complexity, but it does not significantly reduce signal loss and crosstalk. Although the Spanke's network eliminates the crosstalk problem, it increases the number of switching elements required considerably (to 2N ² - 2N). In this paper, we propose a new architecture for building nonblocking optical switching networks that has much lower signal loss and crosstalk than the crossbar without increasing switch complexity. Using this architecture we can build non-squared nonblocking networks that can be used as building block for the Clos network. The resulting Clos network will then have not only lower signal loss and crosstalk but also a lower switch complexity.     

片上网络路由器的交叉开关设计实现

交叉开关是片上网络路由器的关键部分。交叉开关的设计可以采用三态触发器或多路复用器实现。本文针对几种不同形式的交叉开关实现方案,比较了其面积和功耗的开销,同时设计了基于iSLIP算法的交叉开关调度机制。通过基本逻辑门搭建的多路复用器实现的交叉开关相比于采用三态门实现的交叉开关,在功耗、面积上有较大优势。采用iSLIP算法实现的片上网络交叉开关,具有最高的工作频率上限。     

基于VME总线多ADSP21160芯片的通用信号处理模块

利用通用信号处理模块构建信号处理系统的硬件平台已经成为雷达信号处理系统的发展方向 ,介绍了一种通用信号处理模块 ,该模块基于AD公司高性能浮点DSP芯片 ADSP2 1160 ,采用可靠性高、开放性好、通用性强的VME总线作为外部接口。分析了该模块的结构、性能、接口 ,总结了DSP开发、设计、应用中的经验 ,并给出了一个应用实例 ,该模块已经得到了广泛应用     

An evolution to crossbar switches with virtual output queuing and buffered cross points

Input queued (IQ) switch architectures with virtual output queues (VOQ) scale up to very high speeds and have been a subject of intense research in the past decade. VOQ IQ switches require switch matrix scheduling algorithms to match input ports to out ports. In this tutorial article, we present an overview of switch matrix scheduling for VOQ IQ switches with crossbar switch fabrics. We then describe what we believe will be the next generation of high-speed crossbar switches: the evolution of IQ switches to combined input and crossbar queued (CICQ) switches. With the continued increase in density of VLSI, sufficient buffering at crossbar cross points for one cell or packet has become feasible to implement. We show how CICQ switches have simple schedulers and result in lower delay than IQ switches. Both IQ and CICQ switches have unstable regions. We show how a threshold and bursting technique can feasibly achieve stability. We also show how CICQ switches are better suited (than IQ switches) for switching of variable-length packets such as IP packets. Many challenges remain in IQ and CICQ switches. In particular, the inclusion of QoS scheduling methods that are currently only suitable for output queued switches is a major open problem.