Design tradeoffs between surface and buried-channel FET's

A study of the operation of surface- and buried-mode p-channel FET's is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance.     

A simple punchthrough voltage model for short-channel MOSFET's with single channel implantation in VLSI

Based on the step-profile approximation and geometrical analysis, the punchthrough voltage of short-channel enhancement n-channel MOSFET's with single channel implantation has been derived by defining a punchthrough depth. The punchthrough depth, which represents the distance of the two-dimensional potential ridge from the SiO2-Si interface, is calculated by the surface potential of the punchthrough point. Therefore, the derived punchthrough voltage model is then analytically expressed in terms of device geometries and implant parameters. Comparisons between the developed model and the experimental devices have been made and excellent agreement has been obtained.     

A new method for extracting the counter-implanted channel profileof enhancement-mode p-MOSFETs

A new methodology is proposed to extract the nonuniform channel doping profile of enhancement mode p-MOSFETs with counter implantation, based on the relationship between device threshold voltage and substrate bias. A selfconsistent mathematical analysis is developed to calculate the threshold voltage and the surface potential of counter-implanted long-channel p-MOSFET at the onset of heavy inversion. Comparisons between analytic calculation and two-dimensional (2-D) numerical analysis have been made and the accuracy of the developed analytic model has been verified. Based on the developed analytic model, an automated extraction technique has been successfully implemented to extract the channel doping profile. With the aid of a 2-D numerical simulator, the subthreshold current can be obtained by the extracted channel doping profile. Good agreements have been found with measured subthreshold characteristics for both long- and short-channel devices. This new extraction methodology can be used for precise process monitoring and device optimization purposes     

Bulk charge effects in VLSI MOSFET's

An analysis of the relative magnitudes of the bulk charge for three MOSFET structures suitable for VLSI devices, such as NMOS (normal), VMOS (V slot) and UMOS (U slot), is carried out. It is shown that even for the same channel design (i.e. channel length, doping, source/drain junction depth, and oxide thickness), the amount of bulk charge and hence the threshold voltage can be significantly different for the three structures. This effect becomes more important with decreasing channel length, and increasing source to substrate bias. Further, for a given channel length, the bulk charge and hence the threshold voltage of an NMOS decreases with increasing source/drain junction depth. However, for the VMOS and UMOS structures, the bulk charge as well as the threshold voltage do not depend on the junction depth of the source/drain diffusion. An expression is also derived for the bulk charge of UMOS transistors valid for both short and long channels.     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs

In this paper, a fundamental investigation on short-channel effects (SCEs) in 4H-SiC MOSFETs is given. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (0001) and (1120) faces. In the fabricated MOSFETs, SCEs such as punchthrough behavior, decrease of threshold voltage, deterioration of subthreshold characteristics, and saturation of transconductance occur by reducing channel length. The critical channel lengths below which SCEs occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths obtained from the device simulation is in good agreement with the empirical relationship for Si MOSFETs. The critical channel lengths in the fabricated SiC MOSFETs are slightly longer than simulation results. The dependence of crystal face orientations on SCEs is hardly observed. Impacts of interface charge on the appearance of SCEs are discussed.     

A two-dimensional analytical subthreshold behavior model for short-channel AlGaAs/GaAs HFETs

Based on the minimum heteroface potential through an evanescent-mode analysis of two-dimensional potential distribution, the comprehensive and accurate expressions for the short-channel threshold voltage and subthreshold swing for self-aligned gated AlGaAs/GaAs HFETs are developed. It is found that the 2-D electron gas is strongly affected by the DIBL effect which will significantly influence the subthreshold behavior of the AlGaAs/GaAs HFETs. Besides the doping density, the thickness of the spacer and doped body can aggressively affect the short-channel subthreshold behavior comprising threshold voltage shift and subthreshold swing degradation. This model not only gives physical insights into the short-channel effects in HFETs but also offers basic designing guideline for the small-geometry AlGaAs/GaAs HFETs.     

Multiple Sb ion implantation for deep-submicron pMOS channel doping

We propose a channel doping technology for pMOSFET's in which Sb is multiply ion implanted to produce a uniform doping profile in the region deeper than the minimum projected range of the multiple ion implantation. We derive a threshold voltage model and show how to realize this uniform doping profile, which is verified with experimental data. We study the short-channel effect of this device using a two-dimensional (2-D) device simulator, and show that this transistor can readily operate with a gate length of down to 0.1 μm     

Geometrical factors in avalanche punchthrough erase

It is known that the surface potential of an IGFET can be raised to high levels by reverse-bias pulsing its source and drain. This high surface potential is contingent upon both punchthrough and avalanche injection of majority carriers into the surface region. Erase of some multilayer charge storage memory cells is accomplished using such an avalanche punchthrough erase (APTE) operation. In this paper the maximum surface potential achievable in this manner is assessed for a variety of geometries. The calculation is based upon a Fourier sine transform solution of Poisson's equation, coupled with the sampling theorem for spatially localized functions. The depletion width is determined self-consistently and is found to vary from a minimum value at mid-channel to a maximum value at the channel ends. It is found that the maximum surface potential is achieved for devices whose junction depth is comparable to or greater than the channel length. Under these conditions the surface potential can be as large as the reverse bias less the punchthrough voltage. To avoid serious short-channel behavior during normal read operations, it is suggested that the conditionNl^{2} > 2V_{D}kisin_{0}/ebe observed, whereN= doping level/cm³,l= half channel length, VD= drain voltage during read, K = dielectric constant of semiconductor, ∈0= permittivity of free space,e= electronic charge. Thus for a 2-µm channel length we recommend a junction depth ≥2 µm, and a doping level ≈6.5 × 10¹⁵/cm³for a memory cell which is to use APTE and a read voltageV_{D} simeq 5V.     

A two-dimensional analytical threshold voltage model for MOSFET's with arbitrarily doped substrates

A threshold voltage model is presented which is valid for short- and long-channel MOSFET's with a nonuniform substrate doping profile. The model is based upon an approximate two-dimensional analytical solution of Poisson's equation for a MOSFET of arbitrary substrate doping profile which takes into account the effect of curved junctions of finite depth. The analytical model is compared to MINIMOS simulations showing that it can accurately predict short-channel threshold voltage falloff and threshold voltages in this vicinity without the use of fitting parameters.     

Inverse-narrow-width effect of deep sub-micrometer MOSFETs with LOCOS isolation

The effect of scaling down the channel width on the threshold voltage of deep submicron MOSFETs with LOCOS isolation has been investigated. Previous results, obtained from 1 μm technology and above, show an increase in threshold voltage as the width is reduced. However, in deep submicron technology, oxide thickness is scaled-down and channel doping is increased to avoid punchthrough and maintain a sufficiently high threshold voltage. This results in a threshold voltage reduction as channel width is scaled-down—the so called Inverse-Narrow-Width-Effect (INWE). The trend is explained through dopant redistribution and is verified by both experiment and process simulation. Lastly, a new narrow width threshold voltage model is proposed to account for the dopant redistribution effect.     

Tradeoff between threshold voltage and breakdown in high-voltage double-diffused MOS transistors

The design of junction isolated DMOS transistors suitable for monolithic integration has been studied. The purpose of this correspondence is to describe one of the key tradeoffs when designing these devices for high breakdown voltages (200 V for our example). It is a tradeoff primarily between threshold voltage and the punchthrough voltage of the channel diffusion, however, the avalanche breakdown voltage, on-resistance, and source-to-substrate punchthrough voltage are also affected. As an example, the design of a device for 200-V operation is described. The discussion is, however, general and can be applied to other DMOS designs as well.     

Short-channel MOSFET's in the punchthrough current mode

Results of two-dimensional device analysis are compared with experiment for 0.8-µm Si-gate ion-implanted MOS devices operated under conditions of punchthrough transport. Characterization of the punchthrough mode of device operation (a critical factor which limits the maximum drain voltage of submicron MOS VLSI devices) with experiment and simulation has shown that the observed power-law dependence of IDSversusV_{DS} (V_{GS} = V_{SB} = 0)is related to the drain-induced barrier-height lowering. Results of the simulation show the dependence of the punchthrough current upon the range and maximum doping level of the channel implantation. Increasing the substrate-bias or applying a negative-gate voltage is shown to increase the punchthrough voltage. This simulation, which combines results of the process-simulation program (SUPREM) and device-simulation program (CADDET), is shown to predict the behavior of this mode of operation where previous one-dimensional theory has failed.     

Two-dimensional analytical modeling of threshold voltages of short-channel MOSFET's

We present an analytical model of the threshold voltage of a short-channel MOSFET based on an explicit solution of two-dimensional Poisson's equation in the depletion region under the gate. This model predicts an exponential dependence on channel length (L), a linear dependence on drain voltage (VD), and an inverse dependence on oxide capacitance (εox/tox). An attractive feature of this model is that it provides an analytical closed-form expression for the threshold voltage as a function of material and device parameters (tox, VD, L, substrate bias, and substrate doping concentration) without making premature approximations. Also, this expression reduces to the corresponding expression for long-channel devices.     

Threshold voltage of small-geometry Si MOSFETs

This paper uses an accurate, three-dimensional geometrical model for calculation of the threshold voltage of short-channel and narrow-width (small-geometry) silicon MOSFETs. The model expresses the threshold voltage as a function of channel length, channel width, source- and drain-junction depth, backgate bias, drain voltage, gate-oxide thickness and substrate doping concentration. The model also predicts the backgate and drain voltages for punch-through to occur for small-geometry MOSFETs.     

Numerical modeling of power mosfets

The voltage limitations of UMOS vs VDMOS field-effect power transistor structures have been compared using 2-dimensional, 2-carrier numerical simulation for these devices in which the channel doping varies from source to drain. The electric field distribution at the surface and in the bulk is compared for these two structures. Premature voltage breakdown is predicted for the UMOS device caused by impact ionization due to the high electric field near the Si/SiO₂ interface.     

Detailed characterization and analysis of the breakdown voltage infully depleted SOI n-MOSFET's

The breakdown voltage in fully depleted SOI n-MOSFET's has been studied over a wide range of film thicknesses, channel dopings, and channel lengths. In lightly-doped films, the breakdown voltage roll-off at shorter channel lengths becomes much less severe as the film thickness is reduced. This is a result of improved resistance to punchthrough and DIBL effects in thinner SOI. Consequently, at channel lengths below about 0.8 μm, ultrathin (50 nm) SOI can provide better breakdown voltages than thicker films. At heavier doping levels the punchthrough and DIBL are suppressed, and there is little dependence of breakdown voltage on film thickness. Two-dimensional simulations have been used to investigate the breakdown behavior in these devices. It is found that the drain-induced barrier lowering affects the breakdown voltage both directly, via punchthrough, and indirectly through its effect on the current flow and hole generation in the high-field regions     

Simulation and two-dimensional analytical modeling of subthresholdslope in ultrathin-film SOI MOSFETs down to 0.1 μm gate length

The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 μm. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S -factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

An analysis of the threshold voltage for short-channel IGFET''s

For short-channel insulated-gate field-effect transistors (IGFET) operating with source-to-substrate reverse bias, the threshold voltage is in general a function of channel length and drain-to-source voltage. It is shown in this analysis that these dependences can be attributed to the two-dimensional distribution of the depletion charges. Starting from two fundamental relations, the overall charge neutrality and the voltage relations based on the energy band diagram, a generalized threshold voltage equation in integral form is derived. A closed-form threshold equation is then obtained using a regional approximation with a simplified piecewise-linear depletion profile. The equation includes as new factors, the channel length, junction depth and drain voltage, and passes to the conventional form for increasing channel length.

The theoretical threshold voltage expression is found to predict the correct tendencies and is shown to be in reasonable agreement with experimental measurements.