High mobility nanocrystalline silicon transistors on clear plastic substrates

We demonstrate nanocrystalline silicon (nc-Si) top-gate thin-film transistors (TFTs) on optically clear, flexible plastic foil substrates. The silicon layers were deposited by plasma-enhanced chemical vapor deposition at a substrate temperature of 150/spl deg/C. The n-channel nc-Si TFTs have saturation electron mobilities of 18 cm/sup 2/V/sup -1/s/sup -1/ and transconductances of 0.22 /spl mu/S/spl mu/m/sup -1/. With a channel width to length ratio of 2, these TFTs deliver up to 0.1 mA to bottom emitting electrophosphorescent organic light-emitting devices (OLEDs) which were fabricated on a separate glass substrate. These results suggest that high-current, small-area OLED driver TFTs can be made by a low-temperature process, compatible with flexible clear plastic substrates.     

Polycrystalline silicon thin film transistors fabricated in various solid phase crystallized films deposited on glass substrates

In this work, we have characterized various types of polysilicon films, crystallized upon thermal annealing from films deposited by low pressure chemical vapor deposition in the amorphous phase and a mixed phase using silane or in the amorphous phase using disilane. Polysilicon thin film transistors (TFTs) were fabricated, at low processing temperatures, in these three types of films on high strain point Corning Code 1734 and 1735 glass substrates. Double layer films, with the bottom layer deposited in a mixed phase and the top in the amorphous phase, allowed TFT fabrication at a drastically reduced thermal budget; optimum values of thicknesses and deposition rates of the layers are reported for reducing the crystallization time and improving film quality. Optimum deposition conditions for TFT fabrication were also obtained for films deposited using disilane. The grain size distribution for all types of films was shown to be wider for a larger grain size. Fabricated TFTs exhibited field effect electron mobility values in the range of 20 to 50 cm²/V·s, subthreshold swings of about 0.5–1.5 V/dec and threshold voltage values of 2–4 V.     

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors (TFTs) with different channel lengths were realized. The NMOS enhancement load saturation mode (NELS) inverters were prepared by plasma-enhanced chemical vapor deposition at temperatures below 200 °C. The realization of microcrystalline silicon thin-film inverters facilitates the direct integration of column and row drivers and circuitry on display backpanels. The influence of the transistor properties and underlying contact effects on the performance of the inverters will be discussed.     

Thin-film transistors fabricated with poly-Si films crystallized atlow temperature by microwave annealing

Solid phase crystallization of amorphous silicon films for poly-Si thin film transistors (TFTs) has advantages of low cost and excellent uniformity, but the crystallization temperature is too high. Using a microwave annealing method, we lowered the crystallization temperature and shortened the crystallization time. The complete crystallization time at 550°C was within 2 h. The device parameters of TFTs with the poly-Si films crystallized by microwave annealing were similar to those of TFTs with the poly-Si films crystallized by conventional furnace annealing. The new crystallization method seems attractive because of low crystallization temperature, short crystallization time, and comparable film properties     

Amorphous silicon thin-film transistors on steel foil substrates

We report the successful fabrication of high-quality a-Si:H thin-film transistors (TFTs) on stainless steel foil substrates. TFTs with an inverted-staggered structure were grown on 200-μm thick stainless steel foil. These TFTs show typical ON/OFF current ratios of 10⁷, OFF currents on the order of 10^-12 A, good linear and saturation current behavior, subthreshold slopes of 0.5 V/decade, and linear channel mobilities of 0.5 cm²/V. In addition, we have demonstrated that these TFTs are capable of withstanding significant mechanical shocks, as well as macroscopic deformation of the substrate, while remaining functional. This work demonstrates that transistor circuits can be made on a flexible, nonbreakable substrate. Such circuits would be highly useful in reflective or emissive displays, and in other applications that require rugged macroelectronic circuits     

Low-loss microwave interconnections by using polymeric based coplanar waveguides on low resistivity silicon substrates

In this paper a new approach to manufacture low losses coplanar waveguide (CPW) lines for microwave and millimeter wave signal processing is presented. A photolithographic process is performed by using SU-8 thick negative photo-resist on low resistivity silicon wafers, to obtain CPW lines elevated with respect to the substrate, in order to take advantages, in terms of propagation losses, from transmission line structures which are almost on-the-air.     

Structurization of submonolayer carbon coatings deposited in a low-pressure microwave plasma on single-crystal silicon

Features of surface structurization of submonolayer carbon coatings deposited in highly ionized ultrahigh-frequency low-pressure plasma on silicon wafers with (111) and (100) crystallographic orientations are studied. It is shown that the size and surface density of nanostructured carbon formations are controlled by the atomic microstructure of the silicon free surface of these crystallographic orientations and its modifications depending on deposition and annealing conditions. We show the fundamental possibility of fabricating integrated columnar nanostructures with surface densities to (4–5) × 10⁹ cm⁻² and higher than 400 nm by highly anisotropic etching using the obtained carbon island nanostructures as a mask coating on singlecrystal (100) silicon.     

Thin-film transistors in polycrystalline silicon by blanket andlocal source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm²/Vs and an ON/OFF current ratio of ~10⁶, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm²/Vs and an ON/OFF current ratio of ~10⁷. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm² /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current     

Inverter circuits on glass substrates based on ZnO-nanoparticle thin-film transistors

The integration technique and the properties of inverter circuits on glass substrates using ZnO nanoparticles as semiconductor material are presented. The inverter device consists of a switching and a load metal–insulator–semiconductor field-effect transistor with poly(4-vinylphenol) as the gate dielectric. Although the semiconductor is deposited by spin-coating of a colloidal ZnO dispersion and the process temperature is limited to 200 °C, the inverters show reasonable maximum peak gains at low power consumption. The maximum peak gain was 6 V/V, whereas the maximum static power dissipation density was less than 26 nW/μm². Additionally, the influence of the geometry ratio as well as of the supply voltage on the device performance has been investigated. With regard to the optical characteristics, the proposed technique leads to circuits with an optical transmittance of up to 80%.     

Thin-film silicon formation on foreign substrates by rapid thermal chemical vapour deposition for photovoltaic application

Polycrystalline silicon thin-film layers were deposited on foreign substrates such as SiO₂, alumina, mullite and graphite. The deposition studies were carried out in a single-wafer, horizontal, rapid thermal chemical vapour phase reactor at temperatures ranging from 900°C to 1250°C at atmospheric pressure. We employed the gas precursor trichlorosilane and the layers were doped with boron from the dopant source trichloroborine rarified in a hydrogen carrier gas. The surface structures and grain sizes of the thin films obtained were evaluated by Nomarski microscopy and scanning electron microscopy characterization methods. X-ray diffraction analyses were used to determine the preferential crystalline orientations at various operational parameters. Furthermore, electrical properties in terms of Hall mobility and lifetimes of the minority carriers were investigated by means of Van-der-Pauw and photoconductivity decay methods, respectively. Generally, it has been shown that at elevated deposition temperatures maximum grain sizes of 3–20 μm for 10-μm thick layers can be found, depending critically on the type of the substrate. For polycrystalline silicon deposited at 1100°C on silicon dioxide, alumina, and graphite substrates, a preferred crystallographic orientation of (220) was observed, implying columnar grain structures. © 1998 John Wiley & Sons, Ltd.     

Carrier lifetimes in silicon epitaxial layers deposited on oxygen-implanted substrates

Carrier lifetimes in silicon epitaxial layers deposited on high-dose oxygen-implanted wafers have been obtained from measurements of diode storage times. A figure of 1.25 ?S was obtained for diodes in the implanted area, compared with 1.75 ?S for diodes outside the implanted area on the same wafer. This marginal degradation of lifetime indicates that the dielectrically isolated structure should be able to support bipolar and dynamic logic devices.     

Bulk and surface passivation of silicon solar cells accomplished by silicon nitride deposited on industrial scale by microwave PECVD

Bulk and surface passivation by silicon nitride has become an indispensable element in industrial production of multicrystalline silicon (mc‐Si) solar cells. Microwave PECVD is a very effective method for high‐throughput deposition of silicon nitride layers with the required properties for bulk and surface passivation. In this paper an analysis is presented of the relation between deposition parameters of microwave PECVD and material properties of silicon nitride. By tuning the process conditions (substrate temperature, gas flows, working pressure) we have been able to fabricate silicon nitride layers which fulfill almost ideally the four major requirements for mc‐Si solar cells: (1) good anti‐reflection coating (refractive index tunable between 2·0 and 2·3); (2) good surface passivation on p‐type FZ wafers (S_eff<30 cm/s); (3) good bulk passivation (improvement of IQE at 1000 nm by 30% after short thermal anneal); (4) long‐term stability (no observable degradation after several years of exposure to sunlight). By implementing this silicon nitride deposition in an inline production process of mc‐Si solar cells we have been able to produce cells with an efficiency of 16·5%. Finally, we established that the continuous deposition process could be maintained for at least 20 h without interruption for maintenance. On this timescale we did not observe any significant changes in layer properties or cell properties. This shows the robustness of microwave PECVD for industrial production. Copyright © 2005 John Wiley & Sons, Ltd.     

Single-crystal silicon transistors in laser-crystallized thin films on bulk glass

High-performance thin-film transistors (TFT) have been fabricated in single-crystal silicon thin films on bulk fused silica. Deposited films of polycrystalline silicon were patterned to control nucleation and growth of single-crystal material in pre-selected areas and encapsulated with a dielectric layer (e.g., SiO2) in preparation for laser crystallization. Patterning also minimized microcracking during crystallization. The patterned silicon layer was crystallized with a scanning CO2laser, which produced islands with preferred crystal orientation. The single crystallinity of the islands was established with transmission electron microscopy after transistor evaluation. The silicon islands were processed with conventional microelectronic techniques to form metal-oxide-semiconductor-field-effect transistors operating in the n-channel enhancement mode. The devices display exceptional electrical characteristics with "low-field" channel mobilities > 1000 cm²/V sec and leakage currents < 10 pA, for a Channel length of 12 µm and width of 20 µm. Achievement of high-performance TFT's with the combined features of microcrack suppression, preferred orientation, and selected-area crystallization render CO2- laser processing of silicon films a viable and versatile basis for a silicon-on-insulator technology.     

17.6% efficient multilayer thin-film silicon solar cells deposited on heavily doped silicon substrates

We report new results for multilayer thin-film silicon solar cells deposited onto electronically inert, heavily doped crystalline silicon substrates. The n-p-n-p-n active layers of a total thickness of 17 μm combined with a 15-μm thick p⁺-type buffer layer were deposited by chemical vapour deposition epitaxially onto a 10¹⁹ cm⁻³ doped Czochralski-grown silicon substrate. The cells fabricated using these layers exhibit an energy conversion efficiency of up to 17.6%, as measured by Sandia National Laboratories, which is the highest efficiency ever achieved for a thin-film silicon cell deposited onto such an electronically inert crystallographic template. An open-circuit voltage of 664.2 mV is also reported, the highest ever for a cell on such substrates.     

Most digital logic circuits in silicon films deposited on sapphire substrates

Details are given of the construction and performance of MOS transistors, logic elements and digital integrated circuits fabricated in silicon layers grown on sapphire substrates and processed on a p-channel enhancement MOST process. P-channel enhancement MOSTs with parameters similar to those of bulk silicon MOSTs, linear resistors with a high sheet resistivity and non-linear resistors are obtained. The use of non-linear resistors is shown to give static logic circuits with operating speeds 2–4 times faster than linear resistors. In addition node capacitance is reduced, the thick oxide MOST is eliminated and dielectric isolation between devices is obtained. Experimental and computer simulated results are given for the performance of a range of logic elements and circuits.     

Surface-normal Fano filters based on transferred silicon nanomembranes on glass substrates

Surface-normal optical filters are reported based on Fano resonances in patterned single crystalline silicon nanomembranes (SiNM), which were fabricated and transferred onto transparent glass substrates using a disruptive wet transfer process. The measured filter transmission results agree well with the design using a three-dimensional finite-difference time-domain technique. Using the SiNM wet transfer and stacking process, vertically stacked ultra-compact surface normal filters, switches, modulators and spectrally-selective photodetectors will become feasible.     

Bias-stress stability of low-voltage p-channel and n-channel organic thin-film transistors on flexible plastic substrates

The bias-stress stability of low-voltage organic p-channel and n-channel thin-film transistors (TFTs) based on five promising organic semiconductors and fabricated on flexible polyethylene naphthalate (PEN) substrates has been investigated. In particular, it has been studied to which extent the bias-stress-induced decay of the on-state drain current of the TFTs is affected by the choice of the semiconductor and by the gate-source and drain-source voltages applied during bias stress. It has been found that for at least some of the organic p-channel TFTs investigated in this study, the bias-stress stability is comparable to that of a-Si:H and metal-oxide TFTs, despite the fact that the organic TFTs were fabricated at significantly lower process temperatures, which is important in view of the fabrication of these devices on plastic substrates.     

Laser-recrystallized silicon thin-film transistors on expansion-matched 800°C glass

Laser-recrystallized silicon thin-film transistors (TFT's) have been fabricated, for the first time, on a novel, potentially low-cost glass substrate, The 0.5-µm-thick silicon films were deposited along with appropiate dielectric layers on Corning Code 1729 glass substrates and recrystallized using an argon ion laser. The n-channel enhancement-mode transistors were made using conventional IC device fabrication procedures modified to have a maximum processing temperature of 800°C. Transistor's made in the recrystallized silicon show field-effect electron mobilities as high as 270 cm²/V.s, approximately 15 times that of comparable devices made in as-deposited polycrystalline-silicon films. The recrystallized silicon devices also exhibit lower threshold voltages and lower leakage currents than do comparable polycrystalline-silicon devices.     

Microwave properties of self-aligned GaAs/AlGaAs heterojunction bipolar transistors on silicon substrates

(Al,Ga)As/GaAs heterojunction transistors (HBT's) grown on Si substrates have been characterized at microwave frequencies and have been found to perform extremely well. For emitter dimensions of 4 × 20 µm², current gain cutoff frequenciesf_{T} = 30GHz and maximum oscillation frequenciesf_{max}of 11.5 GHz have been obtained in a mesa-type structure. These values compare very well with thef_{T} = 40GHz andf_{max} = 26GHz which are the highest reported for HBT's on GaAs substrates in a nonmesa structure with an emitter width of ∼ 1.5 µm. These results clearly demonstrate the potential of HBT's in general at microwave frequencies, as well as the viability of GaAs on Si technology.     

Electromagnetic wave effects on microwave transistors using afull-wave time-domain model

A detailed full-wave time-domain simulation model for the analysis of electromagnetic effects on the behavior of the submicrometer-gate field-effect transistor (FET's) is presented. The full wave simulation model couples a three-dimensional (3-D) time-domain solution of Maxwell's equations to the active device model. The active device model is based on the moments of the Boltzmann's transport equation obtained by integration over the momentum space. The coupling between the two models is established by using fields obtained from the solution of Maxwell's equations in the active device model to calculate the current densities inside the device. These current densities are used to update the electric and magnetic fields. Numerical results are generated using the coupled model to investigate the effects of electron-wave interaction on the behavior of microwave FET's. The results show that the voltage gain increases along the device width. While the amplitude of the input-voltage wave decays along the device width, due to the electromagnetic energy loss to the conducting electrons, the amplitude of the output-voltage wave increases as more and more energy is transferred from the electrons to the propagating wave along the device width. The simulation confirms that there is an optimum device width for highest voltage gain for a given device structure. Fourier analysis is performed on the device output characteristics to obtain the gain-frequency and phase-frequency dependencies. The analysis shows a nonlinear energy build-up and wave dispersion at higher frequencies