微电容超声换能器的前端专用集成电路设计

针对微电容超声换能器(CMUT)微弱电流信号检测的要求,设计了一种用于CMUT的前端专用集成电路——运算放大器(OPA)电路。运算放大器电路采用两级放大结构,第一级采用全差分折叠-共源共栅结构,输出级采用AB类控制的轨到轨输出级,在运算放大器电路反相输入端和输出端通过一个反馈电阻实现CMUT电流信号到电压信号的转换。采用GlobalFoundries 0.18μm的标准CMOS工艺进行了仿真设计和流片,芯片尺寸为226μm×75μm。仿真结果表明,运算放大器的开环增益为62 dB,单位增益带宽为30 MHz,在3 MHz处的输入参考噪声电压为2.9μV/Hz^1/2,电路采用±3.3 V供电,静态功耗为11 mW。测试结果表明仿真与实测结果相符,该运算放大器电路能够实现CMUT微弱电流信号检测功能。     

Fully Differential CMOS Current Feedback Operational Amplifier

This paper presents a new CMOS fully differential current feedback operational amplifier (FDCFOA). The proposed CMOS realization of the FDCFOA is based on a novel class AB fully differential buffer circuit. Besides the proposed FDCFOA circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 400 A. The applications of the FDCFOA to realize variable gain amplifier, fully differential integrator, and fourth order fully differential maximally flat low pass filter are given. The fourth order filter provides 8 dB gain and a bandwidth of 4.3 MHz to accommodate the wideband CDMA standard. The proposed FDCFOA and its applications are simulated using CMOS 0.35 m technology.Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include low voltage analog CMOS circuit design, filtering and applications suitable for VLSI.Inas Awad was born in Cairo, Egypt, in 1971. She received the Bachelor, the M.Sc. and the Ph.D. degrees in Electronics and Communications from Cairo University in 1994, 1997 and 2000, respectively. In 1995, she joined the department of Electronics and Communications, Cairo University, Fayoum-Campus as a teaching assistant and now she is an Assistant Professor at the same department. Her primary research interest is in analog circuits with particular emphasis on current-mode approach and low-voltage low-power CMOS designs.     

Temperature compensated logarithmic peak detector

A temperature compensated logarithmic amplifier for signal strength indicator or automatic gain control applications is presented. The logarithmic function is realized with a current-feedback operational amplifier with a nonlinear diode feedback. The designed BiCMOS current-feedback operational amplifier utilizes a novel circuit topology which makes possible constant 1 MHz bandwidth amplification with closed loop voltage gains up to 60 dB. The offset current of the current-feedback amplifier is cancelled with an active OTA-C feedback loop. The logarithmically amplified signal is further processed by a peak detector and a temperature compensation circuit. The temperature compensation principle is based on a division of two v _BE:s and it is realized with a current controlled variable current mirror. The logarithmic amplifier is fabricated with a 1.2 micron BiCMOS-process with NPN's f_T of 7 GHz. The power consumption of the circuit is 25 mW with a 4.5 V supply voltage.     

The design of fully differential CMOS operational amplifiers without extra common-mode feedback circuits

A new fully differential CMOS operational amplifier (op amp) without extra common-mode feedback (CMFB) circuit is proposed and analyzed. In this op amp, simple inversely connected current-mirror pairs are used as active loads. From the theoretical analysis, it is shown that the common-mode signal can be efficiently suppressed by the reduced effective common-mode resistance of the active load. The proposed op amp with 2 pF capacitance loadings has an open-loop unity-gain bandwidth of 63 MHz, a phase margin 47°, and a dc gain of 67 dB in 3.5µm p-well CMOS technology. The common-mode gain at a single output node can be as low as —38 dB without extra CMFB circuit. Experimental results have successfully confirmed the capability of the efficient common-mode rejection.This work was supported by the United Microelectronics Corporation (UMC), Republic of China, under Grant C80054.     

Novel cross-connected cascode differential amplifier

We report on a novel amplifier circuit–differential cross-connected cascode1 1.?Reported briefly on WSEAS and ICECS Conferences. . Its fundamental distinction from an ordinary differential cascode lies in simultaneous feeding of input signal both to the common emitter (source) and common base (gate) stages, which are cross-connected. Such a connection results in the creation of two loops of positive current feedback. The stability of the amplifier is achieved due to low gain and phase shift in the loops. We show that the input signal is amplified in the input circuit. The input and output impedances are gained significantly as well. The current gain is increased considerably and the bandwidth is essentially expanded. Simulation results of such a cascode designed with IBM BJT sige5am and CMOS bicmos7hp transistors are presented. When compared with the ordinary cascode, the predicted and actually obtained bandwidths proved to be more than twice as wide: 8.6–18.7 GHz and 3.4–8.7 GHz on BJT and CMOS based, respectively.     

A 15-ns 1-Mbit CMOS SRAM

A 1-Mb CMOS static RAM with a 256 K word×4-bit configuration has been developed. The RAM was fabricated using 0.8-μm double-poly and double-aluminum twin-well CMOS technology. A small cell size of 5.2 μm×8.5 μm and a chip size of 6.15 mm×15.21 mm have been achieved. A fast address access time of 15 ns was achieved using novel circuit techniques: a PMOS-load decoder and a three-stage dynamic gain control sense amplifier combined with an equalization technique and feedback capacitances. A low active current of 50 mA at 20 MHz and low standby currents of 15 mA (TTL) and 2 μA (CMOS) were also attained     

A 5.2 GHz low-voltage low-noise amplifier with 0.35 μm CMOS technology

A low-voltage CMOS low-noise amplifier (LNA) architecture is presented. We have used a TSMC 0.35?µm CMOS high-frequency model to design a fully integrated 1?V, 5.2?GHz two-stage CMOS low-noise amplifier for RF front-end applications. No off-chip element is needed and a conventional common-source with feedback technology is used in this circuit. The first stage of the LNA is the common-source with feedback structure and the output stage is a buffer which increases the gain somewhat. An interstage negative-impedance circuit is added between the two stages of the LNA to further enhance the overall gain and thus upgrade its performance. Mainly because of the finite Q of the inductor, the negative-impedance circuit used in this interstage can cancel the losses in the first-stage inductor load. The input and output matching network is matched to approximately 50?Ω. The simulation results show that the amplifier provides a gain of 9.48?dB, a noise figure of 4.08?dB, and draws 13.4?mW from a 1?V supply. The S11 and S22 are both lower than ?15?dB.     

A Switched Opamp-Based Bandpass Filter: Design and Implementation in a 0.35 μm CMOS Technology

A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 m CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 W. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges.     

A New Approach to Realize Variable Gain Amplifiers

A new methodology to develop variable gain amplifiers is developed. The methodology is based on a feedback loop to generate the exponential characteristic, which is required for VGA circuits. The proposed idea is very suitable for applications that require very low power consumption, and as an application, a new current mode variable gain amplifier will be shown. The gain is adapted via a current signal ranges from –7.5 A to +6.5 A. Pspice simulations based on Mietec 0.5 m CMOS technology show that the gain can be varied over a range of 29.5 dB, with bandwidth of 3 MHz at maximum gain value. The circuit operates between ±1.5 V and consumes an average amount of power less than 495 W.     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

A new design topology for low-voltage CMOS current feedback amplifiers

A new topology for designing low-voltage current feedback amplifiers (CFAs) is presented. By employing a second-generation positive current conveyor followed by an operational amplifier in an unconventional manner, the design circumvents the problem of trying to achieve large transimpedance in a low-voltage environment. It is shown that this CFA configuration also results in near gain independent closed-loop bandwidth defined by a single feedback resistor. The proposed amplifier was verified experimentally by a chip designed using Taiwan Semiconductor Manufacturing Company's 0.18-/spl mu/m digital CMOS process of a single-ended power supply of 1.8 V.     

一种带增益提高技术的高增益CMOS运算放大器的设计

给出了一种用在高速高精度流水线型模数转换器中的具有高增益和高单位增益频率的全差动CMOS运算放大器的设计,电路结构主要采用折叠式共源共栅结构,并采用增益提高技术提高放大器的增益。共模反馈电路由开关电容共模反馈电路实现。模拟结果显示,其开环直流增益可达到106 dB,在负载电容为2 pF时单位增益频率达到了167 MHz,满足了对模数转换器的高速度和高精度的要求。     

New topology for implementing bandpass,bandstop and allpass filters with CFAs

In this brief, a new filter topology based on current feedback amplifiers is presented and compared with its operational amplifier counterpart. The circuits arising from the new topology have the important advantage that access to the Z node of the current feedback amplifier is not required, as is the case with many existing current feedback amplifier filter circuits. The operation and requirements for each of the filters are described. Theoretical results and circuit limitations are discussed and verified with experimental results. In one experiment a bandpass filter with a calculated Q and centre frequency of 20 and 158.53 kHz, respectively was built using the OPA2607 dual CFAs IC. Measured results yielded a Q of 20.153 at a centre frequency of 148.62 kHz showing close agreement with theory.     

A CMOS VGA With DC Offset Cancellation for Direct-Conversion Receivers

A CMOS dB-linear variable gain amplifier (VGA) with a novel I/Q tuning loop for dc-offset cancellation is presented. The CMOS dB-linear VGA provides a variable gain of 60 dB while maintaining its 3-dB bandwidth greater than 2.5 MHz. A novel exponential circuit is proposed to obtain the dB-linear gain control characteristics. Nonideal effects on dB linearity are analyzed and the methods for improvement are suggested. A varying-bandwidth LPF is employed to achieve fast settling. The chip is fabricated in a 0.35- $mu{hbox {m}}$ CMOS technology and the measurement results demonstrate the good dB linearity of the proposed VGA and show that the tuning loop can effectively remove dc offset and suppress I/Q mismatch effects simultaneously.      

一种dB线性数字控制可变增益放大器的设计

设计了一种dB线性增益的数字控制可变增益放大器。以二极管做负载的全差分输入共源极放大器为原型,通过同时同比例地改变输入输出晶体管尺寸比和偏置电流比来控制增益变化,使输入输出晶体管的电流密度保持一恒定值,提高了电路在低增益时的线性度。电路采用NEC 0.35μm CMOS标准工艺库进行设计。仿真结果表明,dB线性增益范围为-11.85dB到11.64dB,增益误差小于0.5dB。增益为-11.85dB时,其1-dB压缩点达到8.35dBm,-3dB增益带宽大于62MHz,并且随设定的增益值在62MHz和240MHz之间变化。     

An Inductorless 300 MHz Wideband CMOS Power Amplifier

The power amplifier tends to be one of the most demanding parts to fully integrate when building an entire radio on a CMOS chip. In this paper the design of a fully integrated RF power amplifier without inductors is described. As inductors in CMOS technology are associated with various problems, it is interesting to examine what performance can be achieved without them. An amplifier with an operating band from 60 MHz to 300 MHz (–3 dB) is built in 0.8 m CMOS. A 3 V supply is used. The measured midband power gain is 30 dB with 50 resistive source and load impedance. As linearity is important for many modern modulation schemes, the amplifier is designed to be as linear as possible. The measured third order intercept point is 23 dBm and the 1 dB compression point is 10 dBm, both referred to the output. The output is single ended to avoid an off-chip differential to single ended transformer.     

Low‐Voltage CMOS Current Feedback Operational Amplifier and Its Application

A novel low‐voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail‐to‐rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ±0.75 V with a total standby current of 304 µA. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ±1 mA. An application of the CFOA to realize a new all‐pass filter is given. PSpice simulation results using 0.25 µm CMOS technology parameters for the proposed CFOA and its application are given.     

A CMOS inverter-based class-AB pseudo-differential amplifier with current-mode common-mode feedback (CMFB)

This paper presents a CMOS inverter-based class-AB pseudo-differential amplifier comprising current-mode common-mode feedback (CMFB). The circuit employs two CMOS inverters and the complementary CMFB consisting of current-mode common-mode (CM) detector and transimpedance amplifier. The circuit has been designed using 0.18 μm CMOS technology and operates at 1 V supply. The simulation results demonstrate rail-to-rail operation with low CM gain (?15 dB). The power dissipation of the circuit is 102.5 μW.     

CMOS fully differential second-generation current conveyor

The design of a CMOS fully differential second generation current conveyor is presented. The proposed circuit was designed to incorporate the current sensing technique into a fully differential version of a differential difference amplifier (DDA). A low power class AB circuit realisation has been implemented in 1.2 μm CMOS technology. A variable gain amplifier (VGA) designed to incorporate the circuit has been shown to exhibit constant, low power consumption and constant, wide bandwidth at different gain settings. Experimental results of the proposed circuits are presented     

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-/spl mu/m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.