High-Performance Chemical-Bath-Deposited Zinc Oxide Thin-Film Transistors

Solution-processed transparent zinc oxide (ZnO) transistors are demonstrated using a chemical bath deposition process for ZnO deposition. The process is glass compatible and amenable to producing fully transparent electronics. Mobility as high as 3.5 cm²/V ldr s with on-off ratios of ~10⁵ is realized. The transparency of ZnO allows for complete coverage of the pixel by the pixel drive transistors; analysis shows that the performance achieved herein is sufficient even to drive high-brightness organic light-emitting diode (OLED) displays by exploiting the high mobility and optical transparency of these devices. This makes this technology extremely attractive for use in active-matrix OLED display applications.     

Carbon-Incorporated Amorphous Indium Zinc Oxide Thin-Film Transistors

We propose the use of amorphous-carbon indium zinc oxide (a-CIZO) as a channel material for thin-film transistor (TFT) fabrication. This study chose a carbon dopant as a carrier suppressor and strong oxygen binder in amorphous-indium zinc oxide (a-IZO) channel material. a-CIZO thin films were deposited using radiofrequency (RF) sputtering and postannealed at 150°C. X-ray diffraction and transmission electron microscopy analysis revealed that the film remained amorphous even after postannealing. The a-CIZO TFT postannealed at 150°C exhibited saturation field-effect mobility of 16.5 cm² V^?1 s^?1 and on–off current ratio of ～4.3 × 10⁷.     

Fully Patterned Low‐Voltage Transparent Metal Oxide Transistors Deposited Solely by Chemical Spray Pyrolysis

All‐inorganic transparent thin‐film transistors deposited solely by the solution processing method of spray pyrolysis are reported. Different precursor materials are employed to create conducting and semiconducting species of ZnO acting as electrodes and active channel material, respectively, as well as zirconium oxide as gate dielectric layer. Additionally, a simple stencil mask system provides sufficient resolution to realize the necessary geometric patterns. As a result, fully functional low‐voltage n‐type transistors with a mobility of 0.18 cm² V^?1 s^?1 can be demonstrated via a technique that bears the potential for upscaling. A detailed microscopic evaluation of the channel region by electron diffraction, high‐resolution and analytical TEM confirms the layer stacking and provides detailed information on the chemical composition and nanocrystalline nature of the individual layers.     

Active Layer Thickness Effects on the On-State Current and Pulse Measurement at Room Temperature on Deposited Zinc Oxide Thin-Film Transistors

This study reports on the fabrication of thin-film transistors (TFTs) with transparent zinc oxide (ZnO) semiconductors serving as the active channel and silicon dioxide (SiO₂) serving as the gate insulator. The ZnO films were deposited by radiofrequency magnetron sputtering at room temperature. Moreover, the effects of channel thickness on the structural and pulse current?Cvoltage characteristics of ZnO TFTs using a bottom gate configuration were investigated. As the channel thickness increased, the crystalline quality and the channel conductance were enhanced. The electrical characteristics of TFTs exhibited field-effect mobilities of 8.36?cm²/Vs to 16.40?cm²/Vs and on-to-off current ratios of 10⁸ to 10⁷ for ZnO layer thickness of 45?nm and 70?nm, respectively. The threshold voltage was in the range of 10?V to 31?V for ZnO layer thicknesses from 35?nm to 70?nm, respectively. The low deposition and processing temperatures make these TFTs suitable for fabrication on flexible substrates.     

Trapping Time Characteristics of Carriers in a-InGaZnO Thin-Film Transistors Fabricated at Low Temperatures for Next-Generation Displays

The effect of low-temperature annealing treatment for various durations on the stability of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors was investigated. By this treatment, IGZO TFTs showed enhanced electrical characteristics and better stability under positive gate bias stress with increasing annealing time up to 18,000 s. For all V _G stresses at different annealing times, the experimentally measured threshold voltage shift (ΔV _th) as a function of stress time was precisely modeled with a stretched-exponential function. ΔV _th was generated by carrier trapping, not by defect creation. It was verified that the decrease of interface trap state density (N _it) and free carriers resulted in the decrease of ΔV _th with increasing annealing time. However, the characteristic trapping time of the carriers increased up to 5.3 × 10³ s with increasing annealing time to 7,200 s and then decreased, implying that the interface quality between active layer/insulator was deteriorated with further annealing. In this study, successful fabrication of IGZO TFTs by post treatment with optimized duration is demonstrated for flexible display applications.     

HgTe Nanocrystal-Based Thin-Film Transistors Fabricated on Glass Substrates

HgTe nanocrystal-based thin-film transistors (TFTs) with Al₂ O₃ top-gate dielectrics were fabricated on glass substrates using sintered HgTe nanocrystals as the channel layers. To the best of our knowledge, this is the first report on the fabrication of nanocrystal-based TFTs on glass substrates. Colloidal HgTe nanocrystal films were first formed on the glass substrates by spin-coating. The HgTe nanocrystal films were then sintered at 150 degC, leading to a dramatic increase in their conductance, compared with the as-deposited films. The TFTs fabricated in this letter exhibit the typical characteristics of p-channel transistors with a field-effect mobility of 1.04 cm²/Vmiddots, a threshold voltage of +0.2 V, and an on/off current ratio of 1times10³. These results suggest that spin-coating and sintering at a low temperature enable the simple and low-cost fabrication of nanocrystal-based TFTs on glass substrates     

溶液法制备环保型高分子聚合物薄膜晶体管

基于一种新型的稠合噻吩-吡咯并吡咯二酮聚合物半导体(PTDPPTFT4),采用溶液法工艺制作了高性能环保型、空穴型有机薄膜晶体管。通过尝试不同的半导体层退火温度及退火时间,优化了有机薄膜晶体管的性能。当采用对二甲苯溶剂,退火温度为190℃,退火时间为60min时,迁移率为2.1cm2·V-1·s-1,电流开关比大于106。通过X射线掠入射角衍射法测试,得到高温退火后聚合物薄膜的结构特点,进而揭示了退火条件改变后,薄膜晶体管拥有高迁移率的原因。     

Phosphorus Doping Effect in a Zinc Oxide Channel Layer to Improve the Performance of Oxide Thin-Film Transistors

In this study, we fabricated phosphorus-doped zinc oxide-based thin-film transistors (TFTs) using direct current (DC) magnetron sputtering at a relatively low temperature of 100°C. To improve the TFT device performance, including field-effect mobility and bias stress stability, phosphorus dopants were employed to suppress the generation of intrinsic defects in the ZnO-based semiconductor. The positive and negative bias stress stabilities were dramatically improved by introducing the phosphorus dopants, which could prevent turn-on voltage (V _ON) shift in the TFTs caused by charge trapping within the active channel layer. The study showed that phosphorus doping in ZnO was an effective method to control the electrical properties of the active channel layers and improve the bias stress stability of oxide-based TFTs.     

High Performance Bottom-Gate-Type Amorphous InGaZnO Flexible Transparent Thin-Film Transistors Deposited on PET Substrates at Low Temperature

The InGaZnO channel layer of bottom-gate-type flexible transparent thin-film transistors was deposited on polyethylene terephthalate substrates using a magnetron radio frequency cosputter system with a single InGaZnO target. The composition of the InGaZnO channel layer was controlled by sputtering at various Ar/O₂ gas ratios. A 15-nm-thick SiO _y insulator film was used to passivate the InGaZnO channel layer. Much better performances of the passivated devices were obtained, which verified the passivation function. To study the bending stability of the resulting flexible transparent thin-film transistors, a stress test with a bending radius of 1.17 cm for 1,500 s was carried out, which showed a variation in the effective filed-effect mobility and the threshold voltage of the unpassivated and passivated devices being maintained within 10 and 8%, respectively.     

Performance Improvement of Organic Thin-Film Transistors by Solution-Processed Crystallization of Pentacene at Room Temperature

Organic thin-film transistors (OTFTs) have been locally grown using solution-phase crystallization of pentacene at room temperature. For crystals grown on the surface, carrier mobility was measured to be approximately 3.0 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ with on/off ratios above $hbox{10}^{6}$. V-shape trenches in the substrate helped to localize the crystallization to within the trenches, and these devices showed similar performance to the surface-grown crystals. This letter suggests that quality OTFT devices may be manufactured using low-cost scalable techniques at room temperature.      

Pentacene-Based Thin-Film Transistors With a Solution-Process Hafnium Oxide Insulator

Pentacene-based organic thin-film transistors with solution-process hafnium oxide (HfOx) as gate insulating layer have been demonstrated. The solution-process HfOx could not only exhibit a high-permittivity (kappa = 11) dielectric constant but also has good dielectric strength. Moreover, the root-mean-square surface roughness and surface energy (gammas) on the surface of the HfOx layer were 1.304 nm and 34.24 mJ/cm², respectively. The smooth, as well as hydrophobic, surface of HfOx could facilitate the direct deposition of the pentacene film without an additional polymer treatment layer, leading to a high field-effect mobility of 3.8 cm²/(V middots) .     

Vertical n-Channel Poly-Si Thin-Film Transistors With Symmetric S/D Fabricated by Ni-Silicide-Induced Lateral-Crystallization Technology

We have successfully developed and fabricated the vertical n-channel polycrystalline silicon thin-film transistors with symmetric S/D fabricated by Ni-silicide-induced lateral-crystallization technology (NSILC-VTFTs). The NSILC-VTFTs are S/D symmetric devices and equivalent to dual-gate devices. The dual-gate structure of NSILC-VTFTs can moderate the lateral electrical field in the drain depletion region, significantly reducing the leakage current. In NSILC-VTFTs, the Ni accumulation and grain boundaries induced from S/D sides can be centralized in the $hbox{n}^{+}$ floating region. The effects of Ni accumulation in symmetric VTFTs crystallized by NSILC and metal-induced lateral crystallization are studied. In addition, a two-step lateral crystallization has been introduced to improve the crystal integrity through secondary crystallization. The NSILC-VTFTs crystallized by two-step lateral crystallization show a steep subthreshold swing of 180 mV/dec and field effect mobility $mu = hbox{553} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ without $hbox{NH}_{3}$ plasma treatment.      

Low Subthreshold Swing HfLaO/Pentacene Organic Thin-Film Transistors

We have integrated a high-kappa HfLaO dielectric into pentacene-based organic thin-film transistors. We measured good device performance, such as a low subthreshold swing of 0.078 V/dec, a threshold voltage of -1.3 V, and a field-effect mobility of 0.71cm²/ Vldrs . This occurred along with an ON-OFF state drive current ratio of 1.0 times 10⁵, when the devices were operated at only 2 V. The performance is due to the high gate-capacitance density of 950 nF/cm² that is given by the HfLaO dielectric, which is achieved at an equivalent oxide thickness of only 3.6 nm with a low leakage current of 5.1 times 10^-7 at 2 V.     

Improvement in the Bias Stability of Zinc-Tin Oxide Thin-Film Transistors by Hafnium Doping

The influence of hafnium (Hf) doping on negative-bias temperature instability in zinc-tin oxide thin-film transistors was studied. Hafnium-zinc-tin oxide TFTs exhibited a turn-on voltage (V _ON) that shifted from 0 V to ?1 V with negligible changes in the subthreshold swing and field-effect mobility after 3 h of total stresses. The enhanced improvement of the V _ON shift (ΔV _ON) was attributed to the reduction in the interface trap density, which may result from the suppression of oxygen-vacancy-related defects by the Hf ions.     

Solution-Processed Zinc Oxide Transistors for Low-Cost Electronics Applications

Transparent conductive oxides are promising candidates for realization of transparent electronics for display applications. The use of solution-processing techniques allows for a dramatic reduction in cost per unit area of electronic functionality. As a result, there is tremendous interest in the use of solution-processed transparent conductive oxides for realization of low-cost transparent electronic systems. Zinc oxide is processable out of solution using a variety of routes, including the use of nanoparticles, nanowires, and chemical bath deposition. By optimizing the deposition processes, it is possible to realize solution-processed transparent semiconductor films offering performance that is comparable to or better than amorphous silicon, while offering the advantages of transparency. Here, techniques for fabrication of solution-processed ZnO-based transistors are reviewed, and the outlook for such technologies is discussed.      

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced     

有机介质层铟锌氧化物薄膜晶体管

利用直流磁控溅射方法在玻璃基板上室温制备非晶铟锌氧化物半导体薄膜,薄膜表面平整。采用旋涂法室温制备聚四乙烯苯酚有机介质层。以铟锌氧化物薄膜作为沟道层、聚四乙烯苯酚作为介质层,成功制备了顶栅结构的薄膜晶体管。测试结果表明,所制备的薄膜晶体管具有饱和特性且为耗尽工作模式,薄膜晶体管的阈值电压为3.8V,迁移率为25.4cm2.V-1.s-1,开关比为106。     

Stretchable,Transparent Zinc Oxide Thin Film Transistors

Stretchable and transparent thin film transistors (TFTs) with intrisically brittle oxide semiconductors are built using a wavy structural configuration that can provide high flexibility and stretchability. After device fabrication procedures including high temperature annealing, the oxide semiconductor‐based TFT arrays can be transferred directly to plastic or rubber substrates, without an additional device process, using transfer printing methods. This procedure can avoid some of the thermal degradation problems associated with plastic or rubber substrates by separating them from the annealing procedure needed to improve the device performance. These design and fabrication methods offer the possibility of developing a new format of stretchable electronics.     

Magnesium Oxide Nanowires Synthesized at Low Temperature by Vapor-liquid-solid Mechanism

Magnesium oxide(MgO) nanowires were synthesized on the gold-coated Si(100) and MgO(100) substrates at lower temperature(600℃) by pulsed liquid injection metal organic chemical vapor deposition(MOCVD). The gold catalyst could be found on the tips of nanowires, which presents the vapor-liquid-solid(VLS) growth mechanism. Reactive species(oxygen or magnesium) have strong effects on the growth of nanowires. Abundant reactive species kill the vertically aligned nanowires to be randomly aligned ones or even chan...