An 8-bit 1 GS/s folding and interpolating ADC with a base-4 architecture

A base-4 architecture for folding and interpolating ADC is proposed. It employs cascaded folding and interpolating topology with both the folding factors and interpolating factors of 4. Duo to that the base-4 folding and interpolating has an intrinsic relationship with the quantization process which is base-2, the architecture requires only 2 × N + 6 comparators for an N-bit ADC. What’s more, the coarse flash ADC can be eliminated because all the most significant bits can be conveniently extracted from the intermediate signals as the “byproduct” of the folding amplifiers. In addition, the base-4 architecture can be extended to higher resolution easily because of the modularized and unified configuration. This architecture is implemented with a 1 GS/s 8-bit ADC in 0.35 μm SiGe BiCMOS process. Measurement results reveal the chip exhibits DNL of 0.30/?0.26 LSB and INL of 0.80/?0.80 LSB. The ENOB is 6.9 LSB at 10.1 MHz input. The SNDR is above 42 dB over the first and the second Nyquist zone. The SFDR is above 45 dB over the first Nyquist zone and the second Nyquist zone. The ERBW is over 1.2 GHz.     

A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm² active area, fabricated in 0.35-μm CMOS     

A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC

This work proposes a four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC based on various analog techniques to minimize mismatches between channels without any calibration scheme. The proposed ADC eliminates an input SHA to reduce offset mismatches, while the pipelined SAR architecture solves the problem of limited input bandwidth as observed in conventional SHA-free ADCs. In addition, a shared residue amplifier between four channels minimizes various mismatches caused by amplifiers in the first-stage MDACs. Two types of references for the residue amplifier and the SAR ADCs isolate the reference instability problem due to different functional requirements, while the shared residue amplifier uses only a single reference during the amplifying mode of each channel to reduce a gain mismatch. For high performance of the SAR ADC, high-frequency clocks with a controllable duty cycle are generated on chip without external, complicated, high-speed multi-phase clocks. The prototype 11 b ADC in a 0.13 μm CMOS shows a measured DNL and INL of 0.31 LSB and 1.18 LSB, respectively, with an SNDR of 59.3 dB and an SFDR of 67.7 dB at 100 MS/s, and an SNDR of 54.5 dB and an SFDR of 65.5 dB at 150 MS/s. The ADC with an active die area of 2.42 mm² consumes 46.8 mW at 1.2 V and 150 MS/s.     

A 9-bit 2 MS/s 1 mW CMOS cyclic folding A/D converter for battery management system

In this paper, a 9-bit 2 MS/s CMOS cyclic folding A/D converter (ADC) for a battery management system is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding–interpolation architecture. The prototype ADC is implemented with a 0.35 μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48 and 60 dB, respectively, and the power consumption is about 1 mW at 3.3 V.     

Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC

This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is ? 0.6/+ 0.67 LSB and INL is ? 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.     

A 14–10 b dual-mode low-noise pipeline ADC for high-end CMOS image sensors

This work proposes a low-noise four-stage pipeline ADC operating at 14 b 50 MS/s and 10 b 70 MS/s for high-end CIS applications. In the 10 b 70 MS/s mode, the last-stage MDAC and flash ADC are turned off rather than the first-stage MDAC and flash ADC for the same input-referred noise in both modes. The proposed ADC shares a single amplifier for the first- and second-stage MDACs to reduce power consumption and chip area. The amplifier thermal noise of the SHA and MDACs is minimized by adjusting the trans-conductance of input and current-source transistors while two separate reference voltage drivers for the MDACs and the flash ADCs reduce the switching noise. The prototype ADC in a 0.13 μm CMOS technology providing 0.35 μm thick-gate-oxide transistors shows the measured DNL and INL within 0.79 and 2.54 LSB in the 14 b mode, and 0.53 and 0.44 LSB in the 10 b mode, respectively. The ADC shows the maximum SNDR and SFDR of 68.5 and 86.7 dB in the 14 b 50 MS/s mode, and the SNDR and SFDR of 60.5 and 77.8 dB for the 10 b 70 MS/s mode, respectively. The ADC with the measured input-referred noise of 1.20 LSB_rms/14 b consumes 192.9 mW at the 14 b 50 MS/s, and 184.9 mW in the 10 b 70 MS/s mode with 3.3/1.2 V dual supplies.     

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at P_in = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

A 53mW IQ pipelined ADC for WLAN front end

This paper presents an analog to digital converter (ADC) architecture suitable for wideband wireless receiver system. The in-phase (I) and quadrature (Q) ADCs work independently, but share on-chip reference buffer and non-overlapped clock generation block for balance between two channels. The single ADC core consists of one front sample and hold amplifier, four cascade of 2.5 bit pipeline stages with pseudo-class AB opamp shared between adjacent stages and one 2 bit backend flash stage. The prototype was fabricated in standard 130 nm CMOS process and occupied silicon area of 0.62 mm². Performance of 66 dB spurious-free-dynamic-range is measured at 80 MS/s with 1 Vpp input signal. The power dissipation of the whole chip is only 53 mW from a 1.1 V supply.     

A High Gain,Low-Power Low-Noise Amplifier for Ultra-Wideband Wireless Systems

This paper presents a high gain, low-power common-gate ultra-wideband low-noise amplifier employing a simple configuration for wideband input matching. In our design, a series resistance-inductance network at the source combines with the parasitic capacitance of a transistor to form a parallel RLC input matching configuration in the common-gate input stage. Because of the additional resistance, this matching configuration partially alleviates the restriction of transconductance of the input transistor and also provides wideband matching. The low-noise amplifier was fabricated using the TSMC 0.18  \(\mu \) m technology with an average noise figure of 3.75 dB, a power gain of 18.68 dB with a ripple of \(\pm \)  0.8 dB, an input return loss less than \(-10\)  dB from 3 to 7.6 GHz, and DC power consumption of 8.56 mW, including the output buffer with a 1.8 V supply voltage.     

1–8 GHz high efficiency single-stage travelling wave power amplifier

This paper describes a Class-A/AB wideband power amplifier that comprises of a single-stage transistor travelling wave structure in which capacitive coupling and frequency dependent lossy artificial-line are employed at the input of the active device. The proposed technique significantly enhances the amplifier’s gain-bandwidth product, input match and gain flatness performance. To ensure the amplifier delivers a predefined power to the load over its entire operating band 2-to-8 GHz a broadband load-pull technique was applied at the output of the amplifier. To avoid reduction in the amplifier’s bandwidth resulting from parasitic capacitive effects associated with the off-chip choke inductor a wideband RF choke was designed. The 1.31 × 2.93 mm² power amplifier was fabricated using 0.25 μm GaAs pHEMT MMIC process. The measurement results show that the proposed amplifier delivers an average P _sat of 29.5 dBm and P _out,1 dB of 26 dBm, and the corresponding PAE levels are 55 and 35 % for the P _sat and P _out,1 dB, respectively.     

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum \(S_{21}\) gain of 11.4 dB gain with a \(-\)3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured \(S_{11}\) and \(S_{12}\) are less than \(-\)10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip

This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of \(-\,2\). Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is + 2/? 1 LSB and the INL is + 1.8/? 1.4 LSB, respectively. Under an 8-bit resolution and a 62.5 Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is \(1.6\,\upmu\)A under a 2.5 V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of \(400 \times 500\,{\mathrm{mm}}^2\).     

Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

A new technique for improving the performance of low-voltage folding ADC’s by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input–output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power dissipation of only 30 mW.     

A 132 Mb/s, 1bit 4224 M samples/s sub-sampling, low-complexity and energy-efficient BPSK transceiver for all-digital 3–5 GHz IR-UWB

In this paper, a 3–5 GHz impulse radio ultra wideband BPSK transceiver is presented. A new all-digital architecture is applied in the proposed transceiver. The transceiver has no mixer and low complexity. The transmitter employs a RLC network response filter to achieve the adjustable pulse parameters, which includes pulse width, pulse bandwidth and pulse amplitude. Considering the low duty ratio, a proposed on/off output buffer in the transmitter is applied to save the power consumption. To simplify the receiver, the radio frequency input signal is amplified and sampled directly by a 1bit 4224 MHz sub-sampling ADC. The ADC comprises by 16 paralleled comparators for low power. Each comparator operates at 264 MHz and can be self-calibrated. The transceiver is implemented in SMIC 0.13 μm CMOS process at the supply of 1.2 V. The measured results show the adjustable parameters: the pulse amplitude is from 110 to 370 mV, the pulse width is from 900 to 1,600 ns and the pulse bandwidth is from 2.0 to 2.78 GHz. The data rate is 132 Mb/s between the transceiver. The transmitter and the receiver only consume 18.2 and 330 pJ/pulse, respectively. The receiver sensitivity is ?75 dBm at the bit error rate of 10^?3.     

Digital background calibration of charge pump based pipelined ADC

In the presented work, digital background calibration of a charge pump based pipelined ADC is presented. A 10-bit 100 MS/s pipelined ADC is designed using TSMC 0.18 µm CMOS technology operating on a 1.8 V power supply voltage. A power efficient opamp-less charge pump based technique is chosen to achieve the desired stage voltage gain of 2 and digital background calibration is used to calibrate the inter-stage gain error. After calibration, the ADC achieves an SNDR of 66.78 dB and SFDR of 79.3 dB. Also, DNL improves to +0.6/–0.4 LSB and INL improves from +9.3/–9.6 LSB to within ±0.5 LSB, consuming 16.53 mW of power.     

An 8-b 100-MSample/s CMOS pipelined folding ADC

Although cascading reduces the number of folders used in folding analog-to-digital converters (ADCs), it demands wider bandwidth. The pipelining scheme proposed in this work greatly alleviates the wide bandwidth requirement of the folding amplifier. The pipelining is implemented with simple differential-pair folders. The key idea is to use odd multiples of folders with distributed interstage track/holds cooperatively with an algorithm for coding and digital error correction for the nonbinary system. The pipelined folding ADC prototyped using 0.5-μm CMOS exhibits a differential nonlinearity (DNL) of ±0.4 LSB and an integral nonlinearity (INL) of ±1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm×1.2 mm in active area and consumes 165 mW at 5 V     

A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications

This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 mum CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which additional switches are introduced to reduce the crosstalk between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths. A symmetrical gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.57 least significant bit (LSB) and 0.8 LSB, respectively, at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V power supply and occupies 0.7 mm², which also includes the bandgap and buffer amplifiers. The figure-of-merit (FOM) of this ADC is 0.26 pJ/step.     

A 10-b 120-MS/s 45?nm CMOS ADC using a re-configurable three-stage switched amplifier

A 10-b 120-MS/s pipeline analog-to-digital converter (ADC) is implemented in a 45?nm CMOS process. Three-stage amplifiers based on reversed nested Miller compensation and Multipath zero cancellation techniques are employed in the input sample-and-hold amplifier (SHA) and two multiplying digital-to-analog converters (MDACs). A single re-configurable three-stage switched amplifier is shared between two adjacent MDACs without MOS series switches and memory effects by employing two separate NMOS input pairs. A charge redistributed input sampling network properly handles both single-ended and differential SHA inputs with a swing range of 1.2?Vpp around a 1.6?V common-mode voltage. The prototype ADC with an active die area of 0.58?mm² consumes 61.6?mW at 120?MS/s and 1.1?V. The measured differential and integral nonlinearities are within ±0.44 and ±0.75?LSB, respectively. At a sampling rate of 120?MHz with a 4.2?MHz sinusoidal input, the measured maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range are 55.6 and 70.4?dB, respectively.