CMOS current-mode pseudo-exponential function circuit

A current-mode analogue circuit that implements a pseudo-exponential function is proposed. The design of the circuit is based on Taylor's series approximation, using MOS transistors in the saturation region. The advantage of this circuit is that the output current presents a very low temperature coefficient (TC) and is also immune to the body-effect. Simulation and experimental results show that the circuit offers a maximum output range of ~30 dB, with an error of less than 1 dB and TC=-233 ppm/°C     

Thin-film strained-SOI CMOS Devices-physical mechanisms for reduction of carrier mobility

We have examined physical mechanisms responsible for the reduction in both electron and hole mobility in strained-silicon-on-insulator (SOI) CMOS devices with thin strained-Si layers. A slight decrease in the electron mobility with thinning strained-Si layers is attributable to the quantum-mechanical confinement effect of the inversion layer electrons, originating in the conduction band offset of the strained-Si layers. Also, the diffusion of Ge atoms into the SiO/sub 2//strained-Si interface is found to generate interface states near the valence band edge, leading to the reduction in hole mobility in the lower E/sub eff/ region through Coulomb scattering. Moreover, the decrease in hole mobility enhancement in both thin and thick strained-Si structures at the higher electric field is caused by the reduction of the energy splitting between the heavy and the light hole bands, with an increase in the electric field. Based on considerations of these factors affecting the mobility reduction, the strained-Si thickness and the Ge content have been designed to realize high-speed strained-SOI CMOS under the 90-nm technology and beyond.     

Algorithmic analogue-to-quaternary convertor circuit using current-mode CMOS

A new current-mode CMOS algorithmic analogue-to-quaternary data convertor circuit has been realised in a standard polysilicon-gate CMOS technology. This circuit accepts an analogue current input and develops a set of quaternary, base-four, output currents. A single type of convertor cell may be cascaded to the desired number of quaternary output digits. The reference current that defines the full scale input range may be set externally. This circuit is input-output compatible with other previously described VLSI-compatible current-mode CMOS quaternary threshold logic and memory circuits.<>     

Extending the functionality of a flexible current-mode CMOS circuit

A current-mode cell based on the square-law characteristic of MOS transistors in saturation is revisited to extend its functionality. The original structure was reported to provide a squaring operation. However, by biasing the circuit differently the circuit can perform the inverse operation and operate as a geometric-mean/square-rooter. This is illustrated with experimental results     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

An integrated CMOS current-sensing circuit for low-Voltage current-mode buck regulator

An integrated current-sensing circuit for low-voltage buck regulator is presented. The minimum achievable supply voltage of the proposed current-sensing circuit is 1.2 V implemented in a CMOS technology with V/sub TH/=0.85 V, and the current-sensing accuracy is higher than 94%. With the developed current-sensing circuit, a buck regulator, which is able to operate at a 1.2-V supply, is implemented. A maximum output current of 120 mA and power-conversion efficiency higher than 89% are achieved.     

A very high-speed CMOS 4-2 compressor using fully differential current-mode circuit techniques

This paper presents a new high-speed CMOS 4-2 compressor which is an essential part in fast digital arithmetic integrated circuits. Current-mode techniques have been used to improve the overall performance of the compressor. New fully differential proposed circuit improves speed up to 45% also reduces occupied area in comparison to other high-speed conventional compressor circuits. To evaluate the performance of the proposed circuit, two other structures have been chosen and all of the circuits have been simulated in 0.18 μm standard TSMC CMOS process with 1.8 V power supply voltage.     

CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques

A CMOS analogue current-mode multiplier/divider circuit is presented. It is based on a dynamic biasing applied at the bulk terminal of MOS transistors operating in both saturation and triode. With the proposed structure, the multiplier forms a feedback loop that improves the current swing and accuracy. The multiplier has been fabricated using a standard 0.18 µm CMOS technology. The circuit consumes 144 µW using a single supply voltage of 1.8 V with a measured THD lower than 1% for an output current of 38 µA, and requires a die area of 90 µm x 45 µm.     

Power-efficient metastability error reduction in CMOS flash A/Dconverters

A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 ⁿ-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 ^-12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10^-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2ⁿ-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs     

A high-precision current-mode WTA-MAX circuit with multichipcapability

This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), loser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication and comparison. Traditional techniques rely on the matching of an N transistors array, where N is the number of system inputs. This implies that when N increases, as the size of the circuit and the distance between transistors will also increase, transistor matching degradation and loss of precision in the overall system performance will result. Furthermore, when multichip systems are required, the transistor matching is even worse and performance is drastically degraded. The technique presented in this paper does not rely on the proper matching of N transistors, but on the precise replication and comparison of currents. This can be performed by current mirrors with a limited number of outputs. Thus, N can increase without degrading the precision, even if the system is distributed among several chips. Also, the different chips constituting the system can be of different foundries without degrading the overall system precision. Experimental results that attest these facts are presented     

A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digitalconverter using fully-differential current-mode circuit techniques

Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-μm n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 db (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm²/b, respectively     

Low-voltage CMOS current-mode exponential circuit with 70 dB output dynamic range

The paper proposes new accurate exponential circuits, having a multitude of practical applications in analog signal processing. The original method for obtaining the exponential function is based on the utilization of new superior-order approximation functions. The accuracy of the proposed structures is excellent and the output dynamic range is strongly extended as a result of the fourth-order approximation and of the independence of implemented function on technological errors and on temperature variations (the best original proposed architecture of the exponential generator has an output dynamic range of 70 dB for an approximation error smaller than ±1 dB). The exponential circuits are designed for implementing in 0.18 µm CMOS technology, having a low-voltage operation (a minimal supply voltage of 1 V). The power consumptions of the proposed exponential circuits are smaller than 0.08 mW, for a supply voltage of 1 V. As application of the new exponential circuit, a dB-linear VGA circuit with high output dynamic range will be presented. The new computational structures have the possibility of generating any continuous mathematical function, presenting also an increased modularity and controllability and reduced design costs per implemented function.     

A CMOS current-mode design of modified learning-vector-quantization neural networks

A modification of LVQ model, Modified LVQ (MLVQ) model, is proposed for the estimation of centroid in pattern recognition. Computer simulation results are presented which demonstrate the behavior of the MLVQ model in estimating the class centroid by utilizing the distance-dependent step size. The results indicate the high potential of less dependence on the initial point as well as the precise settlement of the weight vectors to the centroids. The main feature is that the proposed model is robust to the noise perturbation between two pattern distributions in practical applications.To take advantage of this MLVQ model with the faster training and recalling process for patterns, a hybrid analogdigital processing system is designed by the CMOS current-mode integrated circuit (IC) technology and offers the best attributes of both analog and digital computation. This hybrid processing system operates at microsecond time scale, which enables it to produce real time solutions for complex spatiotemporal problems found in high speed signal processing applications. The overall neural processing system has also been simulated and verified by the HSPICE circuit simulator.     

Charge injection error reduction circuit for switched-currentsystems

The authors propose a novel circuit for reducing the charge injection error based on the technique of current source replication, applied to a second generation memory cell. Using the proposed circuit, offset error, linear gain error, and total harmonic distortion are significantly reduced to the detriment of the occupied die area and the power dissipation which are multiplied by a factor of three     

A new current-mode computational analog block free from the body-effect

In this paper, a new computational/configurable analog block (CAB) is presented based on MOS translinear (MTL) for current-mode nonlinear computation. The proposed CAB architecture consists of three main structures: a new MTL cell, NMOS-PMOS arrays, and two local switch networks. As the new trait, it benefits from an effective compensation technique that extensively minimizes the error generated by body effect–the most important factor amongst the second-order effects. The second feature is that the MTL cell only with six transistors has enabled the CAB to implement more arithmetic functions. This block is capable of implementing such various nonlinear functions as squaring, inverse function, N-dimensional vector summation, full-wave rectifier, four-quadrant multiplier/divider, two-quadrant square-root, and exponential functions. The proposed CAB is simulated with CADENCE and HSPICE software in 0.18 μm TSMC CMOS technology at 1.8 V supply voltage. Most importantly, Post-layout plus Monte Carlo, corner case, and temperature variation simulations are performed to investigate its robust performance in the presence of PVT fabrication non-idealities. Functionality and flexibility of the proposed CAB make it suitable for the core block of Field-Programmable Analog Array (FPAA) ICs and signal processing applications.     

SIMPLIFICATION OF CURRENT-MODE MULTIVALUED CMOS CIRCUITS

This paper proposes a simplification method for realization of current-mode multivalued CMOS circuits. The key of this method is to find a cover on the K-map for a given multivalued function, which fits to the realization of current-mode CMOS circuits. The design example shows that the design presented in this paper is better than the design proposed by G. W. Dueck et al. (1987).     

A low-voltage low-power CMOS fully differential linear transconductor with mobility reduction compensation

A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the proposed transconductor with 0.4V_pp differential input is improved from ?42 dB to ?55 dB while operating from 1.0 V supply. As an example of the applications of the proposed transconductor, a 4th-order 5 MHz Butterworth Gm-C filter is presented. The filter has been designed and simulated in UMC 130 nm CMOS process. It achieves THD of ?53 dB for 0.4V_pp differential input. It consumes 345 μw from 1.0 V single supply. Theoretical and simulated results are in good agreement.