多通道VPX总线固态数据记录回放系统

为满足数字阵列雷达回波数据的实时记录和回放需求,设计并实现了一种多通道VPX总线固态数据记录回放系统。该系统基于ARM-FPGA架构和大容量NAND Flash芯片阵列进行设计,存储容量大,可靠性高,系统设计总记录容量为1.5 TB,总数据记录速率高达640 MB/s,可同时完成4通道光纤数据的实时记录或回放。     

高速雷达数据回放系统的实现

随着航空、雷达、声纳、遥感卫星图像传输等领域实时数据采集量的不断增加，以及实时数据处理系统能力的不断提升，对记录和回放系统的数据传输速率提出了更高的要求。现提出了一种高速雷达数据回放系统的实现方案。采用高性能的磁盘阵列和I／O控制载板，同时结合定制化设计的零延时换序PMC卡，使得单通道数据回放速率可以达到512Mb／s，满足了系统的设计指标。     

高速信号采集记录仪设计

针对高速信号实时采集存储的需求,设计了一种高速信号采集记录仪。记录仪通过高速A/D转换器对信号进行采样,并实时存入NAND FLASH存储阵列中。为提高数据存储速率,综合采用并行总线、交错双平面页编程、多级流水线等技术,大幅提升FLASH的写入速度。记录仪可实现8bit、200MSPS的采样速率,并可将速率为200MB/s的采样数据实时存储。     

ITU-T H.261编解码器及其实现

简要介绍了ITU-TH.261图像压缩编解码原理和所涉及的一些压缩处理方法。并介绍了一种实现方案,可实现64kbits/s～2Mbits/s速率之间的视频压缩编解码,编码速率大于384kbits/s时编解码延时小于0.3秒。     

机载窄带多路视频传输系统设计

为了满足两路视频的实时窄带无线传输要求,设计并实现了一种JlEG2000视频压缩解压缩与多路数据传输系统.系统总线带宽为3.84Mbit/s,视频信号采集、压缩、下传、回放的延时控制在300ms以内.本系统由APV202来完成视频压缩与解压缩,由FPGA来实现两路视频数据和一路遥感数据的封装及传输.用ATmega128...     

基于OSG的船舶及目标航迹管理的设计与实现

采用QT Creator和C++语言开发了基于OSG的船舶及目标航迹管理系统,岸基指挥中心与各船舶通过专用无线网络进行实时数据通信.利用无线网络将船舶及其传感器目标传送至岸基地面指挥中心,岸基船舶及目标航迹管理系统通过OSG提供的谷歌地图将船舶及其传感器目标的位置实时显示电子地图上,利用MYSQL数据库保存船舶及其传感器目标的位置信息,以此实现特定时间段内船舶及目标航迹的回放.     

分析高数据速率时的抖动

随着数据速率超过Gb/s水平,工程师必须能够识别和解决抖动问题.抖动是在高速数据传输线中导致误码的定时噪声.如果系统的数据速率提高,在几秒内测得的抖动幅度会大体不变,但在位周期的几分之一时间内测量时,它会随着数据速率成比例提高,进而导致误码.     

一种采用PCI软核的轴角数据采集系统

研究一种基于PCI软核的轴角编码数据采集系统,实现伺服系统角度位置量的实时测控.采用FPGA器件实现PCI接口逻辑、FIFO存贮单元及轴角转换控制逻辑,采用旋转变压器?数字转换模块实现高速轴角转换,并设计了相应地WDM驱动程序.采集板应用于LabWindows的测控系统中,数据采样速率达到27 r/s,数据传输速率达到132 MB/s.     

高采样率的双踪数字示波器设计

设计了一台具有实时采样和等效采样的数字双踪示波器,AD采样率最高为1 MSa/s(兆采样/秒),最大等效采样率达到1 GSa/s。垂直灵敏度从2 V/div～2 mV/div共10挡;水平扫描速度从100 ms/div～25 ns/div共20挡。电压测量误差和周期测量误差均小于3%。采用内触发方式,上升沿触发,且触发电平可调。具有存储/回放、单次触发、自动设置挡、直流耦合和交流耦合等功能。     

基于SOPC的数字示波器的设计与实现

基于SOPC的数字示波器,结合FPGA和软核NIOSⅡ的优势,采用实时采样和等时效采样两种方法实现对较高频率的测量,系统结构设计中尽量采用低耗时的数据传输方式并充分利用DE1中的资源,采用VGA方式显示波形.该系统测量频率范围为10 Hz～1.5 MHz,实时采样速率≤1 Msample/s,等效采样速率≥200 Msample/s,该系统实现了采样频率的自动调整、数据存储等功能,并具有高速、实时、高频测量准确可靠、便携等特点,具有很好的性能与实用性.     

40 Gbit/s packet bit error ratio and loss real-time measurement for ultrahigh-speed packet switched network

A novel packet bit error rate (BER) and loss measurement method and system is proposed. A proposed 40 Gbit/s packet BER and loss measurement system is expressed in detail. A 40 Gbit/s BER and loss measurement with various conditions is demonstrated experimentally. In real time, only the payload part of a packet and burst stream with fluctuated guard time is evaluated. The BER and packet loss of a randomly received packet sequence due to routing and buffering can be also evaluated by the measurement system. A 10 Gbit/s packet BER and loss measurement with optical label switching, buffering, and preamble-free optical packet 3R are demonstrated experimentally.     

Packet data transmission over mobile radio channels

Since in mobile radio Rayleigh fading poses the main threat to accurate data transmission, a mathematical model of the dynamics of Rayleigh fading is used to explore the optimum duration of data packets. The performance criterion is the rate of information transfer through the mobile radio channel. In addition to packet size, the information rate depends on: the speed of the mobile terminal, the channel bit rate, the size of the packet header, and the fade margin of the modulation and coding techniques. In particular, attention is focused on line rates of 16 kb/s and 256 kb/s (which are representative of the rates proposed for digital mobile radio systems in North America and Europe, respectively). At 16 kb/s, the optimum packet size is approximately 17 B (8.5-ms duration). At 256 kb/s, maximum throughput occurs when the packet contains about 48 B (1.5-ms duration). The precise optimum depends on vehicle speed, header size, and fade margin. The optimum packets are considerably shorter than the 125-B packets customarily used in terrestrial and satellite systems     

A high-capacity broadband packet switch architecture based on a multilink approach

Broadband packet networks based on asynchronous transfer mode (ATM) are expected to provide a wide range of services, including motion video, voice, data and image. When these networks become prevalent, some applications such as motion video and high-speed LAN interconnections will place a very large bit rate requirement on the channels. Currently, the physical layer supported by the synchronous optical network (SONET) allows the transmission of up to 2.4 Gbit/s with the OC-48 optical interface. However, it is not feasible for the electronic packet switch to route packets at this rate on a single link. In this paper we present a design of a broadband packet switch that uses multiple links in parallel to realize a high-speed channel. This implementation permits the switch to operate at the lower link rate, which can be at 150 Mbit/s, while having the ability to support a virtual circuit at a higher rate (up to 2.4 Gbit/s). The main contribution of the design is that packet sequence on a channel is still maintained even though packets are allowed to use any of the links belonging to the same channel. Besides allowing the switch to function at a slower rate than the transmission channel rate, the implementation of the multilinks benefits from statistical multiplexing gain. Analytical results show the performance advantages of multilink design with respect to delay, throughput and packet loss probability.     

155Mb／s时分光交换系统

本文介绍了国内第一个１５５Ｍｂ／ｓ时分光交换实验系统。系统以新型半导体光器件－半导体光开关门为核心构成，传输速度为１５５Ｍｂ／ｓ。     

HSUPA技术及其发展

HSUPA(高速上行分组接入)是3GPP标准化组织为进一步满足数据业务需求在WCDMA/UTRA-FDDR6版本中提出的一种新技术,本文详细描述了引入HSUPA后WCDMA系统结构的演化,阐述了HSUPA中涉及的物理层混合自动请求重传(HARQ)、快速调度、短帧长、新扩频因子以及软切换等关键技术及其相应研究,最后对HSUPA技术及WCDMA的发展趋势进行了讨论.     

All-optical serial header processing based on two-pulse correlation

An all-optical serial header processor is demonstrated using a semiconductor laser amplifier in a loop mirror configuration (SLALOM). The operation of the header processor is discussed and it is experimentally demonstrated with a 10 Gbit/s Manchester encoded (information rate of 5 Gbit/s) packet stream. The operation of the header processor is based on the correlation function of the SLALOM. The header processor can be utilised in devising all-optical packet switches     

High-performance optical-label switching packet routers and smart edge routers for the next-generation Internet

This paper discusses the architecture, protocol, analysis, and experimentation of optical packet switching routers incorporating optical-label switching (OLS) technologies and electronic edge routers with traffic shaping capabilities. The core optical router incorporates all-optical switching with contention resolution in wavelength, time, and space domains. It is also capable of accommodating traffic of any protocol and format, and supports packet, flow, burst, and circuit traffic. The edge router is designed to achieve traffic shaping with consideration for quality of service and priority based class-of-service. Simulation results show packet loss rates below 0.3% at load 0.7 and jitter values below 18 /spl mu/s. The traffic shaping reduces the packet loss rate by a factor of /spl sim/5 while adding negligible additional latency. The OLS core routers and the electronic edge routers are constructed including the field-programmable-gate-arrays incorporating the wavelength-aware forwarding and contention resolution algorithms. The experiment shows optical-label-based packet switching with a packet loss rate near 0.2%.     

Scalable multi-QoS IP+ATM switch router architecture

This article proposes a scalable multi-QoS IP+ATM switch router architecture. The proposed switch router is based on a core ATM switching system with multi-QoS capability. Forwarding engines and a routing engine are attached in front of the line cards of the ATM switching system. The FEs and RE are interconnected with each other via internal VCs. A novel longest matching algorithm is employed at the FE to achieve packet forwarding at wire-speed of OC-12c rate (622.08 Mb/s). Wire-speed unicast and multicast packet forwarding are performed using point-to-point and point-to-multipoint VCs in a unified way. Because FEs and RE are decoupled from the base ATM switching system, the full spectrum of ATM QoS capability is nicely applied for IP QoS control with a packet classification at the edge of the network. The core switching fabric is scalable from 40 to 160 Gb/s capacity (371 MPPS in terms of packet forwarding throughput). Feedback rate control is employed at each line card to eliminate congestion in the high-speed core switching fabric even with a small amount of buffer.     

高速光突发模式接收机设计

介绍了一种高速光突发模式接收机。整形电路采用直流耦合跨阻抗前馈式结构。突发同步恢复电路采用一种新颖的固定相位调节振荡器。仿真表明：在传输速率为1．25Gb／s，误码率BER≤10^-9时，接收灵敏度为-25dBm（平均光功率）。最大可接收光功率-1dBm，动态范围可高达24dB，两分组信号保护时间为20ns。对速率为5Gb／s的NRZ突发数据可在10ps之内建立比特同步。     

Active vertical-coupler-based optical crosspoint switch matrix for optical packet-switching applications

Packet-switching characteristics are optimized across an integrated 4 /spl times/ 4 optical crosspoint switch matrix consisting of active vertical-coupler-based switch cells. Optical gain difference between the shortest and the longest paths less than 3 dB is demonstrated. Bit error rate (BER) and power penalty measurements during packet routing have also been carried out over the entire 4 /spl times/ 4 matrix. At a 10-Gb/s packet data rate, a less than 1-dB power penalty is observed across the switch matrix, and the possibility for error-free packet routing is demonstrated with no BER floor observed.