共查询到19条相似文献,搜索用时 62 毫秒
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近年来60 GHz附近的一个连续频段可以自由使用,这为短距离的无线个域网等高速率传输的应用提供了条件.设计了一个工作在60 GHz的CMOS功率放大器.采用台积电0.13μmRF-CMOS工艺设计制造,芯片面积为0.35mm × 0.4 mm,最大线性输出功率为11 dBm,增益为9.7 dB,漏极增加效率(η_(PAE))为9.1%.达到应用在通信距离为10 m的无线个域网(WPAN)射频电路中的要求.设计中采用了厚栅氧化层工艺器件和Load-Pull方法设计最优化输出阻抗z_(opt),以提高输出功率.该方法能较大提高CMOS功率放大器的输出功率,可以应用到各种CMOS功率放大器设计中. 相似文献
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为了满足短距离无线高速传输的应用需求,基于SMIC 90 nm 1P9M CMOS工艺,设计了一种可工作在60 GHz的功率放大器(PA)。该PA为单端三级级联结构。采用顶层金属方法,设计具有高品质因子的小感值螺旋电感,用于输入、输出和级间匹配电路,以提高电路的整体性能。通过减少传输损耗和输出匹配损耗,提高了附加功率效率。仿真结果表明,在1.2 V电源电压下,该PA的功率增益为17.2 dB,1 dB压缩点的输出功率为8.1 dBm,饱和输出功率为12.1 dBm,峰值功率附加效率为15.7%,直流功耗为70 mW。各性能指标均满足60 GHz通信系统的要求。 相似文献
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提出了一种采用0.13 μm SiGe工艺制作的77 GHz功率放大器。该放大器采用两路合成结构提高输出功率,采用两级差分放大结构提高增益。功率级选择Cascode结构,提升功率级输出阻抗,便于匹配。驱动级选择共射极加中和电容的结构,便于提升增益。在输入端,通过两路耦合线巴伦结构进行功率分配,得到两对差分信号,经过两路放大之后再通过两路耦合线巴伦结构进行功率合成,最后输出信号,级间匹配采用变压器匹配。该功率放大器采用ADS软件仿真。结果表明,在77 GHz的工作频点处,小信号增益为19.6 dB,峰值功率附加效率为11%,饱和输出功率为18.5 dBm。 相似文献
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设计了一种基于65 nm CMOS工艺的60 GHz功率放大器。采用共源共栅结构与电容中和共源级结构相结合的方式来提高功率放大器的增益,并采用两路差分结构来提高输出功率。采用片上变压器作为输入/输出匹配及级间匹配,以减小芯片的面积,从而降低成本。采用Cadence、ADS和Momentum等软件进行联合仿真。后仿真结果表明,在工作频段为60 GHz时,最大小信号增益为26 dB,最大功率附加效率为18.6%,饱和输出功率为15.2 dBm。该功率放大器具有高增益、高效率、低成本等优点。 相似文献
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分析了一种射频COMS共源-共栅低噪声放大器的设计电路,采用TSMC 90nm低功耗工艺实现。仿真结果表明:在5.6GHz工作频率,电压增益约为18.5dB;噪声系数为1.78dB;增益1dB压缩点为-21.72dBm;输入参考三阶交调点为-11.75dBm。在1.2V直流电压下测得的功耗约为25mW。 相似文献
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A fully monolithically-integrated power amplifier with a bandwidth (-3 dB) from 20.5 to 31 GHz was realised in a 0.13 /spl mu/m standard CMOS technology. A maximum power added efficiency of 13% with a corresponding output power of 13 dBm was achieved at 25.7 GHz with 1.5 V supply voltage. 相似文献
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A fully integrated CMOS differential power amplifier driver(PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements,a transmission line transformer is used as the output matching network.A differential inductance constitutes an inter-stage matching network.Meanwhile,an on chip balun realizes input matching as well as single-end to differential conversion.The PAD is fabricated in a 0.13μm RFCMOS process.The chip size is 1.1×1.1 mm~2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB. 相似文献
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基于片上变压器耦合的CMOS功率放大器设计 总被引:1,自引:0,他引:1
设计了一个2 GHz全集成的CMOS功率放大器(PA),该PA的匹配网络采用片上变压器实现,片上变压器用来实现单端信号和差分信号之间的转换和输入、输出端的阻抗匹配。采用ADS Momentum软件对片上变压器进行电磁仿真,在2 GHz频点,输入、级间和输出变压器的功率传输效率分别为74.2%,75.5%和78.4%。该PA基于TSMC 65 nm CMOS模型设计,采用Agilent ADS软件进行电路仿真,仿真结果表明:在2.5 V供电电压、2 GHz工作频率点,PA的输入、输出完全匹配到50Ω(S11=–22.4 d B、S22=–13.5 d B),功率增益为33.2 d B,最高输出功率达到23.4 d Bm,最高功率附加效率(PAE)达到35.3%,芯片面积仅为1.01 mm2。 相似文献
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Jhon H.-S. Song I. Jeon J. Jung H. Koo M. Park B.-G. Lee J.D. Shin H. 《Electronics letters》2008,44(23):1353-1354
As wireless applications expand, requirements for a radio that can support multi-bands and multi-standards are continuously increasing. In a single-chip radio, a low noise amplifier (LNA) plays an important role in the noise performance or sensitivity of the total receiver chain. Although up to now a number of broadband and dualband LNAs have been reported with good performance in CMOS technology, most previous work has focused on a low frequency range, below 10 GHz. In general a dual-band LNA can be achieved by combining two LNAs in parallel for each narrow band [1]. However, this approach demands twice the power dissipation, a large chip area and therefore a significant increase in cost. Recently the low power and compact-sized dual-band LNA using a switching inductor, capacitor and concurrent method also has been reported [2?4]. In this Letter a low power concurrent dual-band LNA is proposed which is suitable for 17.1?17.3 GHz and 24?24.25 GHz industrial, scientific and medical (ISM) band application. 相似文献
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Yu K.-W. Lu Y.-L. Huang D. Chang D.-C. Liang V. Chang M.F. 《Electronics letters》2003,39(22):1559-1560
A 24 GHz monolithic low-noise amplifier (LNA) is implemented in a standard 0.18 /spl mu/m CMOS technology. Measurements show a gain of 12.86 dB and a noise figure of 5.6 dB at 23.5 GHz. The input and output return losses are better than 11 dB and 22 dB across the 22-29 GHz span, respectively. The operation frequency of 24 GHz is believed to be the highest reported for LNA in a standard CMOS technology. 相似文献
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YunSeong Eo KwangDu Lee 《Microwave and Wireless Components Letters, IEEE》2004,14(11):504-506
A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement. 相似文献
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In this paper, an RF power amplifier intended for class 1 Bluetooth application is designed using 0.35 µm CMOS technology. A layout-aware macromodel for the BSIM3v3 MOSFET transistor for RF applications including substrate effect is investigated and used in this design. The model is validated for a 0.35 μm CMOS process using a transistor with total width of 90 μm and 18 fingers and it shows excellent agreement with the ft and S-parameter measurement data up to 6 GHz. The effects of pads and bond wires are also taken into consideration during the design process of the PA. After post-layout simulations, the amplifier delivers an output power of 19 dBm with 33.7% PAE under 3.3 V supply. This amplifier has a power control feature; its two stage circuit utilizes a cascode configuration in its first stage in order to use its bias pin as a power control input for the amplifier. Using this method, the power control range can be decreased down to 1.4 dBm which satisfies the Bluetooth standard. The chip is fabricated and is currently under testing. 相似文献
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To implement a fully-integrated on-chip CMOS power amplifier(PA) for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency(PAE) is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol. 相似文献