2.5 Gb/s GaAs PIN/PHEMT单片集成光接收机前端

采用0.5 μm GaAs PHEMT工艺,研制了一种PIN光探测器和分布放大器单片集成850 nm光接收机前端. 探测器光敏面直径为30 μm,电容为0.25 pF,10 V反向偏压下的暗电流小于20 nA.分布放大器-3 dB带宽接近20 GHz,跨阻增益约46 dBΩ;在50 MHz～16 GHz范围内,输入、输出电压驻波比均小于2;噪声系数在3.03～6.50 dB之间.单片集成光接收机前端在1.0和2.5 Gb/s非归零(NRZ)伪随机二进制序列(PRBS)调制的光信号下得到较为清晰的输出眼图.     

5Gb/s单片集成GaAs MSM/PHEMT 850nm光接收机前端

采用0.5μm GaAs PHEMT工艺研制出了一种单片集成850nm光接收机前端,它包括金属-半导体-金属(MSM)光探测器和分布放大器.探测器光敏面积为50μm×50μm,电容为0.17pF,4V偏压下的暗电流小于17nA.分布放大器-3dB带宽接近20GHz,跨阻增益约46dBΩ;在50MHz～16GHz范围内,输入、输出电压驻波比均小于2;噪声系数在3.03～6.5 dB之间.光接收机前端在输入2.5和5Gb/s非归零伪随机二进制序列调制的光信号下,得到较为清晰的输出眼图.     

5Gb/s单片集成GaAs MSM/PHEMT 850nm光接收机前端

采用0.5μm GaAs PHEMT工艺研制出了一种单片集成850nm光接收机前端,它包括金属-半导体-金属(MSM)光探测器和分布放大器.探测器光敏面积为50μm×50μm,电容为0.17pF,4V偏压下的暗电流小于17nA.分布放大器-3dB带宽接近20GHz,跨阻增益约46dBΩ;在50MHz～16GHz范围内,输入、输出电压驻波比均小于2;噪声系数在3.03～6.5 dB之间.光接收机前端在输入2.5和5Gb/s非归零伪随机二进制序列调制的光信号下,得到较为清晰的输出眼图.     

一种850 nm单片集成光接收机前端

采用0.5μm GaAs PHEMT工艺和台面光刻互连工艺研制了一种850nm光接收机前端单片电路,包括金属-半导体-金属光探测器和跨阻前置放大器。探测器光敏面积约2000μm2,电容小于0.15pF,4V偏压下的暗电流小于14nA。跨阻前置放大器-3dB带宽接近10GHz,跨阻增益约43dBΩ。光接收机前端在输入2.5Gb/s非归零伪随机二进制序列调制的850nm光信号下得到较为清晰的输出眼图。     

单片集成长波长光接收机

介绍了利用InGaAs 长波长金属-半导体-金属(MSM)光探测器与InAlAs/InGaAs 高电子迁移率晶体管(HEMT)集成来实现长波长单片集成光接收机的材料和电路设计、关键工艺途径等,解决了工艺兼容性问题,实现了2.5Gb/s传输速率下功能正确的单片集成长波长光接收机样品.     

1.25Gb/s InP基多量子阱激光器与HBT驱动电路的单片集成

描述了一种基于InP材料沿[011]晶向湿法化学腐蚀形成平滑侧壁实现的InP基多量子阱激光器和异质结双极晶体管驱动电路单片集成.通过一个横向缓冲台面结构,降低了激光器阳极和晶体管集电极互连工艺的难度,改善了光发射单片光电集成电路的可制造性.采用该方法制作的光发射单片直流功耗为120mW,在码长223-1传输速率1.5Gb/s伪随机码信号调制下有清晰的眼图,光输出功率为2dBm.     

1.25Gb/s InP基多量子阱激光器与HBT驱动电路的单片集成

描述了一种基于InP材料沿[011]晶向湿法化学腐蚀形成平滑侧壁实现的InP基多量子阱激光器和异质结双极晶体管驱动电路单片集成.通过一个横向缓冲台面结构,降低了激光器阳极和晶体管集电极互连工艺的难度,改善了光发射单片光电集成电路的可制造性.采用该方法制作的光发射单片直流功耗为120mW,在码长223-1传输速率1.5Gb/s伪随机码信号调制下有清晰的眼图,光输出功率为2dBm.     

用于单片集成光接收机前端的GaAs基InP/InGaAs HBT

实现了一种可用于单片集成光接收机前端的GaAs基InP/InGaAs HBT。借助超薄低温InP缓冲层在GaAs衬底上生长出了高质量的InP外延层。在此基础上,只利用超薄低温InP缓冲层技术就在半绝缘GaAs衬底上成功制备出了InP/InGaAsHBT,器件的电流截止频率达到4.4GHz,开启电压0.4V,反向击穿电压大于4V,直流放大倍数约为20。该HBT器件和GaAs基长波长、可调谐InP光探测器单片集成为实现适用于WDM光纤通信系统的高性能、集成化光接收机前端提供了一种新的解决方法。     

用于40Gb/s光接收机的0.2μm GaAs PHEMT分布放大器

利用0.2μm GaAs PHEMT工艺实现了40Gb/s光接收机中的前置放大器.该放大器采用有源偏置的七级分布放大器结构,3dB带宽超过40GHz,输入输出反射损耗小于一10dB,跨阻增益为45.6dBΩ,最小等效输入噪声电流密度为22pA/√Hz,功耗为300mW,可有效地应用于40Gb/s光接收机中.     

10Gb/s GaAs PHEMT光接收机前置放大器

简要分析了光接收机分布式前置放大器所具有的宽带优势,研制出了一种利用南京电子器件研究所0．5μm标准GaAs PHEMT工艺实现的10 Gb/s分布式前置放大器。该前置放大器采用损耗补偿技术,由七个共源共栅级联的单元组成,测试结果表明,该分布式前置放大器可以工作在10 Gb/s速率上。     

Compact 2.5 Gb/s Burst‐Mode Receiver with Optimum APD Gain for XG‐PON1 and GPON Applications

This letter presents a compact 2.5 Gb/s burst‐mode receiver using the first reported monolithic amplifier IC developed with 0.25 …m SiGe BiCMOS technology. With optimum avalanche photodiode gain, the receiver module can obtain a fast response, high sensitivity and wide dynamic range, satisfying the overhead timing and various power specifications for a 2.5 Gb/s next‐generation passive optical network (PON), as well as a legacy 1.25 Gb/s PON in the upstream.     

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC     

A monolithic GaAs receiver for optical interconnect systems

A monolithic GaAs optical receiver which includes a photodetector and preamplifier was designed and fabricated using a common 1.0-μm GaAs MESFET technology. The optical receiver operates at the data rate of 1 Gb/s. The transimpedance value can be continuously tuned from 1 to 10 kΩ. The metal-semiconductor-metal photodiode shows a 35% efficiency. Several design factors are considered to achieve high-bandwidth and low-noise operation. An array of the integrated receivers can be compactly implemented in a single chip for high-speed interconnection networks and photonic signal processing     

A monolithic GaAs-on-Si receiver front end for optical interconnectsystems

The authors describe a monolithic technology for integrating GaAs with Si bipolar devices and demonstrate that such integration can provide improved system performance without degrading individual devices. The technology has been used to implement a 1-GHz GaAs/Si optical receiver with an equivalent input noise current density of less than 3 pA/√Hz for midband operation, and less than 4.5 pA/√Hz at 1 GHz. In this receiver an interdigitated GaAs metal-semiconductor-metal (MSM) photodetector is combined with a transimpedance preamplifier fabricated in silicon bipolar technology. The measured dark current of the GaAs/Si photodetector is 7 nA. The measured pulse response of an experimental integrated receiver is less than 550 ps FWHM. The integrated front end provides a wideband, low-noise optical receiver for use in local optical interconnections and demonstrates the successful application of integrated GaAs-on-Si technology to optoelectronics     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.     

Optoelectronic integrated receivers on InP substrates byorganometallic vapor phase epitaxy

The monolithic integrated ion of a p-i-n photodiode and a high-electron mobility transistor (HEMT) amplifier on an InP substrate by organometallic vapor-phase epitaxy is discussed. The receiver operated with up to 1.6 Gb/s nonreturn-to-zero optical signals. The responsivity was 1 kV/W and the minimum optical power at a bit error rate of 10^-9 was -24 dBm for 400 Mb/s nonreturn-to-zero optical signals     

27-GHz bandwidth high-speed monolithic integrated optoelectronicphotoreceiver consisting of a waveguide fed photodiode and anInAlAs/InGaAs-HFET traveling wave amplifier

A monolithic integrated photoreceiver for 1.55-μm wavelength has been designed for operation in a 20-Gb/s synchronous digital hierarchy system (SDH/SONET), based on a new integration concept. The optoelectronic integrated circuit (OEIC) receiver combines a waveguide-integrated PIN-photodiode and a traveling wave amplifier in coplanar waveguide layout with four InAlAs/InGaAs/InP-HFETs (0.7-μm gate length). The receiver demonstrates a bandwidth of 27 GHz with a low frequency transimpedance of 40 dBΩ. This is, to our knowledge, the highest bandwidth ever reported for a monolithic integrated photoreceiver on InP. Furthermore, a receiver sensitivity of -12 dBm in the fiber (20 Gb/s, BER=10^-9) and an overall optical input dynamic range of 27 dB is achieved. Optical time domain multiplex (TDM) system experiments of the receiver packaged in a module show an excellently shaped eye pattern for 20 Gb/s and an overall sensitivity of -30.5 dBm (BER=10^-9) [including erbium doped fiber amplifiers (EDFA)]     

Photonic integration for high-volume, low-cost applications - [Topics in optical communications]

To date, photonic integration has seen only limited use in a few optical interface applications. The recently adopted IEEE draft standards for 40 Gb/s and 100 Gb/s Ethernet single-mode fiber local area network applications will change this situation. Although first generation implementations will use discrete components based on existing technologies, long-term requirements for significant reduction in cost, size, and power of 40 Gb/s and 100 Gb/s transceivers will lead to a broad demand for photonic integration. Both hybrid planar lightguide circuit and monolithic photonic integrated circuit are feasible approaches that meet the requirements of the new IEEE standards.