Bayesian techniques to reduce the sample size in automotive electronics attribute testing

This paper discusses the application of Bayesian techniques to the determination of sample sizes required for an attribute test of a product in order to demonstrate a target reliability with a specified confidence. The method is based on analyzing statistical data on similar products and incorporating them into a Bayesian prior distribution for the unknown reliability. A mixture prior obtained by combining a beta prior with the uniform rectangular prior (representing the unknown content of the new product design) is discussed. The suggested method can significantly lower sample sizes for attribute tests and thus reduce cost, time, and resources currently being spent on reliability demonstration testing. A numerical example at the end of the paper illustrates the method.     

3G核心网技术及规划过程中应考虑的问题

介绍3G核心网络技术标准,分析比较R99、R4两种常见的技术标准,指出了R4技术标准的优点所在,探讨在3G核心网规划中应遵循的原则及应考虑的问题.     

Network planning methodology and practice in China

The methods used in local network planning for the public telecommunications network in China are discussed. Network modeling, computer simulation, and planning software used in the planning process are described. A computer-aided planning tool for local telephone networks (CAPTLN), composed of three software modules that provide traffic forecasting, network optimization, and network economic analysis for the local network of the public switched telephone network (PSTN), is also discussed. Other tools are similarly used for all other parts of the PSTN network, such as international access, toll switching and trunking, signaling and synchronization     

RSFQ circuitry realized in a SINIS technology process

We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j_C=400 A/cm² and a characteristic voltage of V_C=165 μV, the area of the smallest junction is A=24 μm². The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j_C is below ±8%. The margins of the bias current I_b of the circuits have been experimentally determined and found to be larger than ±24%. At preset, constant values of I_b, the range of a separate bias current I_bsw fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than ±56%     

一种有效减少总场—散射场源电磁泄漏的方法

总场-散射场源是时域有限差分法(FDTD)最常用的激励源,但受时域有限差分法电场和磁场数值采样既不同位又不同时的影响,不可避免地会有入射波泄漏到散射场区,从而对计算结果造成影响。文中提出一种减少总场-散射场源电磁泄漏的方法,其基本原理是:在总场区和散射场区的连接界面附近,使用亚网格进行仿真,而在其它区域,使用主网格进行仿真。使用亚网格仿真时,空间步长和时间步长均明显小于使用主网格仿真时的空间步长和时间步长,从而可以明显减小在加入激励源时电场和磁场数值采样既不同位又不同时的影响,大幅度地改善计算结果。编程进行了数值实验,实验结果表明新方法在减少总场-散射场源电磁泄漏方面效果明显。     

A novel technology to reduce the antenna charging effects duringpolysilicon gate electron-cyclotron-resonance etching

A novel technique, which uses Cl₂/O₂ mixed gas in the electron cyclotron resonance (ECR) etching system, has been proposed to remove the antenna charging effect of the MOS capacitors with 5-nm-thick oxides during polysilicon gate etching. The Cl₂ /O₂ can cause the trenching effect and prevents the gate oxide from the charging damage. Furthermore, the ECR system can provide high polysilicon/oxide selectivity so that the Si substrate under gate oxide is not directly bombarded by the ions. Consequently, the E_bd degradation of the MOS capacitors disappears as the trenching effect is apparent by using moderate Cl₂/O₂ mixed gas     

Agent-based distributed manufacturing process planning and scheduling: a state-of-the-art survey

Manufacturing process planning is the process of selecting and sequencing manufacturing processes such that they achieve one or more goals and satisfy a set of domain constraints. Manufacturing scheduling is the process of selecting a process plan and assigning manufacturing resources for specific time periods to the set of manufacturing processes in the plan. It is, in fact, an optimization process by which limited manufacturing resources are allocated over time among parallel and sequential activities. Manufacturing process planning and scheduling are usually considered to be two separate and distinct phases. Traditional optimization approaches to these problems do not consider the constraints of both domains simultaneously and result in suboptimal solutions. Without considering real-time machine workloads and shop floor dynamics, process plans may become suboptimal or even invalid at the time of execution. Therefore, there is a need for the integration of manufacturing process-planning and scheduling systems for generating more realistic and effective plans. After describing the complexity of the manufacturing process-planning and scheduling problems, this paper reviews the research literature on manufacturing process planning, scheduling as well as their integration, particularly on agent-based approaches to these difficult problems. Major issues in these research areas are discussed, and research opportunities and challenges are identified.     

Linux下Oracle应用技术及实现

OCI是一个功能十分强大的数据库操作模块,Libsqlora8 for *nix是GNU/Linux组织针对OCI的易用性开发的C语言封装,文章详细阐述了如何在Linux平台上利用Libsqlora8函数库开发Oracle数据库的过程.     

TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology

The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.     

On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology

The need for a novel multi-scale ESD (ElectroStatic Discharge) network recognition and verification methodology is described in this paper. The proposed solution is used to limit the risk of ESD design errors and to enhance IC reliability, independently of the implemented ESD protection strategy and the type of package assembly technique. This method relies on a topology-aware & graph-based verification paradigm which is generic enough to be usable at every step of the design flow. Its efficiency is illustrated with examples involving custom I/O ring portions in 28nm UTBB FD-SOI High-K metal gate technology.     

TD-LTE网络随机接入前导码规划分析

TD-LTE网络随机接入是终端接入网络的必经过程,是用户进行初始连接、切换、连接重建立以及重新恢复上行同步的唯一策略,其失败率会影响TD-LTE网络的接入性能。本文中重点介绍TD-LTE网络随机接入前导码的精细规划,以及随着网络割接调整而实施的前导码自动规划。     

一种特殊阶梯板制作工艺技术的开发

近年来,随着PCB的迅猛发展,PCB的设计也日新月异。对于阶梯板的制作,目前业界通常是采用low-flow PP压合+控深铣开盖工艺或内层开槽填充硅胶等缓冲材料的工艺生产。介绍了一种采用机械控深铣+CO2激光工艺的特殊阶梯板制作方法。该工艺可缓解常规方法对层压控制的特别要求,而且在运作流程上也得到了一定简化,拓展了常规方法所无法实现的特殊订单制作。     

On a periodic training sequence in DFE to reduce the steady-stateerror probability

A periodic transmission of a short resetting sequence used to “fill up” the decision-feedback equalizer feedback filter memory with correct symbols is proposed to reduce the propagation error. Two strategies are considered: full and partial reset, where the entire memory and some part of it is reset, respectively. For any given steady-state bit-error rate, the period of the resetting sequence is found by use of the Markov chain limit theorem. It is shown, via an illustrative example, that for low signal-to-noise ratio (SNR), the resetting strategy outperforms Bose-Chaudhuri-Hocquenghen (BCH) code with the same code rate. Moreover, a joint resetting and error correction coding strategy is considered, which is better than BCH code for low and medium SNR     

信息科技时代人口老龄化与居住区规划设计

当前,我国人口老龄化趋势越来越严重,不仅是我国经济社会发展必须关注的问题,更是居住区规划设计必须考虑到的因素。本文首先介绍了老龄化的概述及其对居住区规划设计的影响,然后分析了老年人对居住区的需求特征,最后详细探讨了居住区规划设计中应对人口老龄化的措施。     

Material and process limits in silicon VLSI technology

The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years there is great uncertainty about the ability to continue scaling metal-oxide-semiconductor field-effect transistor (MOSFET) structures. This paper describes some of the the most challenging materials and process issues to be faced in the future and where possible solutions are known, describes these potential solutions. The paper is written with the underlying assumption that the basic metal-oxide-semiconductor (MOS) transistor will remain the dominant switching device used in ICs and it further assumes that silicon will remain the dominant substrate material     

Effect of laminated wafer toward dicing process and alternative double pass sawing method to reduce chipping

Thin wafers of 100-/spl mu/m thickness laminated with die-attach film (DAF) was diced using a standard sawing process and revealed a low chipping crack resistance. Wafers laminated with conductive DAF shows greater chipping compared to nonconductive DAF and bare silicon wafer. It was found through scanning electron microscopy (SEM) micrographs, energy dispersive X-ray (EDX) analysis, and atomic force microscopy (AFM) that silver fillers in the conductive DAF was the cause of excessive blade loading which resulted in bad chipping quality. To reduce chipping/cracking induced by sawing, an alternative double-pass sawing method was developed and is explained in the paper. The methodology of this study discusses a double-pass method, where the first pass dice through the wafer and varied the percentage of DAF thickness cut. Best results were achieved when dicing through the wafer and 0% of DAF, followed by a full separation in the second pass. Approximately 80% of chipping reduction compared to conventional single pass.     

一种叠孔三阶HDI板制作技术研究

近年来,由于3G手机的普及和智能手机的出现,推动PCB(Printed Circuit Board,印制电路板)技术不断向前发展,加快HDI类产品的增长需求,尤其是三阶HDI产品将成为3G手机未来的主流,而智能手机则以三阶、any-layer HDI设计为主。这些需求带动HDI技术逐渐向更高布线密度方向发展,线宽线距不断减小,板件结构从1+N+1到stagger-via(交错孔),再到stack-via(叠孔),其制作难度不断加大。因此,对三阶HDI板的制作工艺技术进行研究,掌握叠孔三阶及多阶HDI板制作技术将成为抢占当今市场的关键所在。     

Circuits to reduce distortion in the diode-bridge track-and-hold

Circuits for reducing distortion in the diode-bridge track-and-hold are described. Adding circuits with current and voltage feedback can reduce distortion caused by the droop and nonlinear junction capacitance of a transistor. A high-speed complementary bipolar process technology is incorporated in the circuit design for its flexibility. SPICE II simulation demonstrates that the circuits reduce distortion in the diode-bridge track-and-hold by 10 to 20 dB     

Survey on flash technology with specific attention to the critical process parameters related to manufacturing

In this paper, the history of flash processes will be presented, starting with the 1.2-/spl mu/m technology to the most current technology. The front- and back-end process modules will be reviewed taking into account the main impact on cell functionality and reliability. In particular, the lithographic and mask issues, the diffusion and cleaning process steps, the chemical mechanical planarization technique to improve planarization, and the high-energy and large-tilted implant will be covered. Finally, the process and equipment trends for the next-generation flash technology will be presented.