A switched-capacitor successive-approximation A/D converter

A switched-capacitor successive-approximation analog-to-digital (A/D) converter that incorporates a serial digital-to-analog (D/A) subconverter for generating the threshold voltage sequence is developed. The conversion process is insensitive to parasitic capacitances and offset voltages of the comparator and operational amplifiers. Error analyses and Spice simulations show that a resolution higher than 11 b, a sampling rate up to 440 ksamples/s with 10-b resolution, and a power consumption less than 60 mW are attainable with monolithic implementation using present CMOS technologies. The required chip area is small because of a low device count. The architecture described is therefore best suited for high-accuracy, medium-speed A/D converters in application-specific integrated circuits (ASICs). A prototype converter breadboarded using discrete components has confirmed the principles of operation     

Polarization-switching D/A converter

This paper describes a novel digital-to-analog (D/A) conversion technique, which uses the analog quantity polarization as a D/A conversion medium. It can be implemented by CMOS capacitors or by ferroelectric capacitors, which exhibit strong nonlinearity in charge versus voltage behavior. Because a ferroelectric material inherently has spontaneous polarization and generally has a large dielectric constant, the effective capacitance of a ferroelectric capacitor is much larger than that of a CMOS capacitor of the same size. This ensures less influence of bottom-electrode parasitic capacitance on a ferroelectric capacitor. Furthermore, a data converter based on ferroelectric capacitors possesses the potential nonvolatile memory function owing to ferroelectric hysteresis. Along with the architecture proposed for polarization-switching digital-to-analog converter (PDAC), its circuit implementation is introduced. Described is implementation of two 9-bit bipolar PDACs: one is based on CMOS capacitors and the other on off-chip ferroelectric capacitors. Experimental results are presented for the performance of these two prototypes.     

多数制式混沌A/D变换器研究

从目前的工程观点来看,一个本身不稳定的Ａ／Ｄ变换器是不可能用来进行精确的Ａ／Ｄ变换的。本提出可用极不稳定的混沌电路实现精确稳定的Ａ／Ｄ变换,并且可随意改变为２、３等进制的Ａ／Ｄ变换。虽然其精度目前还未超过现有的Ａ／Ｄ变换器,但这是一种全新意义上的Ａ／Ｄ变换,值得进一步研究。     

A Digitally Programmable A/D Converter for Smart Sensors Applications

Nonlinear analog-to-digital conversion in smart sensor applications is an important topic since signal digitization and linearization can be performed in a single step near the transducer. In this paper a double pulsewidth modulated (PWM) scheme for nonlinear analog-to-digital conversion is presented. Calibration or auto-calibration data stored in the smart sensor's memory define the nonlinear profile characteristic of the transducer and provide the required data to obtain the inverse function of the analog-to-digital converter (ADC) transfer curve. Basically, as a function of the transducer's nonlinearity degree, the input voltage range of the ADC is segmented in a continuous set of subintervals and, for each of these subintervals, a second-order correction term based on a PWM A/D conversion is used to obtain a linear characteristic for the smart sensor. Additional advantages of this method result from its easy implementation in low-cost microcontrollers that include generally comparator inputs and PWM outputs. A flexible and programmable A/D conversion solution can be dynamically adapted to variations of the transducer's nonlinearity profile, and an increased resolution can be achieved at the expense of a lower conversion rate. Some MATLAB simulations and experimental results obtained with a square-root airflow transducer will be presented in the final part of the paper     

High-speed A/D conversion incorporating a QMF bank

A structure for analog-to-digital (A/D) conversion capable of attaining high speed and using an array of lower-speed A/D converters is introduced. The structure is based on a quadrature mirror filter (QMF) bank, except that the analysis filter bank is a switched-capacitor circuit, whereas the synthesis filter bank is normally a digital circuit. It is shown that the effect of mismatches among the A/D converters in the array is considerably reduced by the QMF bank. Simulation and experimental results verifying the good performance of the proposed approach are included     

自适应光学波前处理机D/A电路的优化

为了适应当前的自适应光学系统的要求，介绍一种多路D/A转换电路的优化及实现方法。它将输出的多路数字信号依次地通过一路D/A，进行数模转换，再通过采样保持器，将各路信号进行采样保持，分成了多路信号来控制变形镜，从而不但简化了系统，而且综合小信号误差，减少故障率。     

A/D converter characterization by spectral analysis in“Dual-Tone” mode

Analog-to-digital (A/D) converter performances are constantly improving, concerning both conversion speed and resolution. Consequently, characterization becomes harder as the limits of the testing instrumentation are reached. We tried to answer that problem by defining a test methodology based on “dual-tone” spectral analysis. In this paper we present both the basic principles of this method and also experimental results on A/D converters     

一种提高单片机内嵌式A/D分辨力的方法

单片机内嵌式Ａ／Ｄ的使用要比外置式Ａ／Ｄ简单、方便，且容易获得更高的信噪比，但其分辨力相对比较低，难以满足精密测量的使用要求。本文介绍了一种提高单片机内嵌式Ａ／Ｄ转换器分辨力有效实用法，简单外转电路和单片机内部软件计算可以将原分辨力将提高１￣３倍。     

基于A／D转换原理的铂电阻非线性校正设计

本文介绍一种基于Ａ／Ｄ转换原理的铂电阻非线性校正的设计方法。给出铂电阻线性测温的设计原理和实际电路，运用数学原理对铂电阻测温电路进行研究，为铂电阻的非线性校正方法提供理论依据。最后给出了实验结果。     

Digital correction of A/D conversion error due to multiplexingdelay

A measurement channel which consists of a multiplexer, sample-and-hold circuit, and analog-to-digital (A/D) converter is studied. It is designed for the synchronous sampling and measurement of two or more voltage signals V₁(t), V ₂(t), . . ., but the finite time of A/D conversion (ΔT) makes it impossible to acquire consecutive samples closer in time than ΔT. This can become a source of measurement error if further processing of the measurement data is based on the assumption of ideal synchronism. It has been found that interpolation filters, developed from the Lagrange polynomial interpolation, are useful tools for solving the problem of correction. An illustrative example of their use is presented     

D/A转换器建立时间对输出信号质量的影响

考虑D／A转换器建立时间的影响，建立了D／A转换器输出信号波形的新的时域模型。在此基础上，以正弦信号的发生为例进行了频谱分析。发现了建立过程的平滑作用可以明显地削弱信号的谐波分量，并存在一个最佳转换频率，使谐波失真达到最小值。该结果为D/A信号发生器的优化设计提供了参考依据。     

线阵CCD高速A/D接口技术及开发系统

本文介绍了一种新的不用DMA芯片的高速。A/D数据采集和处理系统,该系统以8098单片机为核心,采用单地址总线,双数据总线的结构。高速A/D采集时,数据流与指令流相分离,A/D结果直接存入相应的RAM区,可达到2MC的采样速率。本文还介绍了由它组成的线阵CCD应用开发系统的特点。此系统可工作在逐位A/D采样测量方式和二值化脉冲测量方式,还可以和286、386微机组成主-从式光信息测控系统。     

Analysis of mismatch effects among A/D converters in atime-interleaved waveform digitizer

High-speed A/D conversion can be achieved by employing a parallel array of M A/D converters interleaved in time, each working at 1/Mth of the sampling rate. Theoretically, the resolution of the structure is given by the resolution of the A/D converters in the array (subconverters). In practice, however, mismatches among the subconverters lead to a decrease in the resolution. The effect of such mismatches is analyzed in terms of a signal-to-noise ratio defined as the ratio between the energy of the input analog signal and the energy of the error signal due exclusively to these mismatches. The analysis shows that the distortion is comparable to that generated by nonuniform sample timing in the analog demultiplexer when converting a single high-speed signal into several low-speed sampled-and-held signals. The results of the analysis can be used to specify the degree of precision to be achieved in an actual monolithic implementation     

A flash Josephson A/D converter constructed with one-junctionSQUIDs

A novel approach to the construction of a flash-type Josephson A/D (analog/digital) converter is presented. Simulations show that one-junction SQUID (superconducting quantum interference device) comparators can have a greater than fivefold advantage in bandwidth over the two- or three-junction SQUIDs in an A/D circuit. Assuming a Nb junction technology, the simulations show that a 6-bit A/D converter using one-junction SQUID comparators could have a sampling rate of ~20 GHz with ~5 bits of resolution for a 5-GHz input signal. Detailed analysis and simulations of an A/D converter constructed with one-junction SQUIDs are presented. Further improvement can be made by using a coding algorithm which requires 2N-1 comparators, instead of N, for an N-bit A/D converter     

Speed-limiting factors in flash-type Josephson A/D converters

The authors discuss the causes of speed limitations in various A/D (analog/digital) converter designs. The upper limit on bandwidth is extracted with the help of Josephson SPICE simulations. In the Josephson A/D converter circuits discussed, the dynamic properties of the SQUIDs (superconducting quantum interference devices) determine the aperture time and dictate the bandwidth. Designs for 4-bit A/D converters that show potential for bandwidths on the order of 10 GHz are described. Particular attention is given to the bit-parallel A/D converter with self-gating AND comparator and bit-parallel A/D converters with CLAM (current latching analog microcomparator) and variable-pulse peak comparators     

介质/金属/介质多层透明导电薄膜研究进展

综述了介质/金属/介质(dielectric/metal/dielectric,D/M/D)多层透明导电膜材料的特点、制备方法、研究进展与应用现状,重点比较讨论了ITO/Ag/ITO、ZnS/Ag/ZnS的膜系结构、光电性能、化学稳定性、热稳定性等特点,以及与国内外的研究差距.ITO/Ag/ITO、ZnS/Ag/ZnS是目前光电性能最好,且无需引入过渡层的两种D/M/D膜系,但有关其热稳定性的评价和研究存在不同的观点.用资源丰富、价格便宜、无毒的掺铝氧化锌(ZAO)薄膜取代含有价格昂贵的贵金属铟的掺锡氧化铟(ITO)薄膜,ZAO/Ag/ZAO膜系结构的设计、薄膜制备、光电性能与IMI的对比研究是目前国内外D/M/D研究中的热点课题和D/M/D发展的主要方向.     

基于对氯苄胺的2D/3D钙钛矿太阳能电池

三维(3D)有机–无机金属卤化物钙钛矿薄膜的表面和晶界处存在大量缺陷,容易导致载流子的非辐射复合并加快3D钙钛矿分解,进而影响钙钛矿太阳能电池(PSCs)能量转换效率(PCE)及稳定性.本研究通过引入对氯苄胺阳离子,与3D钙钛矿薄膜及其表面过剩的碘化铅反应后原位形成了二维(2D)钙钛矿,实现了对3D钙钛矿薄膜表面和晶界...     

Analysis of distortion in A/D converters by time-domain andcode-density techniques

Two new methods for measuring the total harmonic distortion of an A/D converter are described. One is based on time-domain analysis, the other on modified code density analysis. Experiments show that these methods give results comparable to the ones provided by FFT analysis. It is then shown, by both experiments on a flash converter and computer simulations, that the conventional code density analysis does not provide accurate signal-to-noise-plus-distortion ratio (SNDR) estimates at the highest frequencies, while the proposed methods do     

D／A转换器的模型化测试策略

本文提出了模型化测量D/A转换器非线性误差的方法,讨论了建模技术和选择优化试验点的方法。利用这些工具,可以从一组充分、必要的测量数据,准确估计出在所有码态时转换器的非线性误差、位误差和重叠误差。     

Micro/Nanoscale 3D Assembly by Rolling,Folding, Curving,and Buckling Approaches

The miniaturization of electronics has been an important topic of study for several decades. The established roadmaps following Moore's Law have encountered bottlenecks in recent years, as planar processing techniques are already close to their physical limits. To bypass some of the intrinsic challenges of planar technologies, more and more efforts have been devoted to the development of 3D electronics, through either direct 3D fabrication or indirect 3D assembly. Recent research efforts into direct 3D fabrication have focused on the development of 3D transistor technologies and 3D heterogeneous integration schemes, but these technologies are typically constrained by the accessible range of sophisticated 3D geometries and the complexity of the fabrication processes. As an alternative route, 3D assembly methods make full use of mature planar technologies to form predefined 2D precursor structures in the desired materials and sizes, which are then transformed into targeted 3D mesostructures by mechanical deformation. The latest progress in the area of micro/nanoscale 3D assembly, covering the various classes of methods through rolling, folding, curving, and buckling assembly, is discussed, focusing on the design concepts, principles, and applications of different methods, followed by an outlook on the remaining challenges and open opportunities.