Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM

Verifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.     

基于受限随机矢量生成的功能验证

在SOC设计中,传统功能验证方法面临诸多挑战,主要体现在：①复杂验证场景难以构建。②边缘情况难以覆盖。基于受限随机矢量生成的功能验证方法在满足约束条件的前提下,随机产生验证矢量．有效解决了传统验证方法面临的挑战。本文以一款SOC的存储子系统控制模块为例,研究了在Specman验证平台上,使用E语言构建验证环境的基于受限随机矢量生成的功能验证在SOC设计中的应用。验证结果表明,复杂验证场景和边缘情况的覆盖率均达到100％。经过多目标圆片(MPW)流片试验和测试,采用该方法验证的模块达到设计要求。     

Generation of Electrically Induced Stimuli for MEMS Self-Test

A major task for the implementation of Built-In-Self-Test (BIST) strategies for MEMS is the generation of the test stimuli. These devices can work in different energy domains and are thus designed to sense signals which are generally not electrical. In this work, we describe, for different types of MEMS, how the required non-electrical test stimuli can be induced on-chip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The on-chip test signal generation is illustrated for the case of MEMS transducers which exploit such physical principles as time-varying electrostatic capacitance, piezo-resistivity effect and Seebeck effect. These principles are used in devices such as accelerometers, infrared imagers, pressure sensors or tactile sensors. For implementation, we have used two major MEMS technologies including CMOS-compatible bulk micromachining and surface micromachining. We illustrate the ability to generate on-chip test stimuli and to implement a self-test strategy for the case of a complete application. This corresponds to an infrared imager that can be used in multiple applications such as overheating detection, night vision, and earth tracking for satellite positioning. The imager consists of an array of thermal pixels that sense an infrared radiation. Each pixel is implemented as a suspended membrane that contains several thermopiles along the different support arms. The on-chip test signal generation proposed requires only slight modifications and allows a production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.     

一种高效高速的大容量FPGA电路功能验证方法

对大容量FPGA芯片进行功能验证时,如何提高验证效率以及验证用例的覆盖率已经成为缩短总体产品时间所面临的挑战.针对上述问题,提出了一种高效、高速的大容量FPGA电路验证方法,可以根据验证用例需求,利用FPGA预先配置一定的功能,通过采取不同的配置文件得到最优网表.该验证方法具有灵活动态配置网表功能,可以节省仿真资源80％左右,大幅度缩短仿真时间,仿真器运行速度至少提高20倍,同时可以提高验证效率,最大限度地提高验证电路的覆盖率,能够满足大容量电路功能仿真的需求.该验证方法已成功应用于大容量FPGA电路功能验证工程实践中.     

时序机的功能验证

本文介绍了时序电路（时序机）功能验证的基本概念和发展，分析了验证中存在的问题以及冗余故障的性质．提出基于ＳＴＧ的功能验证方法。最后，提出了采用动态任务调度策略的并行验证技术以解决状态遍历问题。     

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST

In the context of analog BIST for ADC, this paper presents two structures for the internal generation of a linear signal used with the histogram-based test technique. All of these structures use wide-swing current mirrors and an original adaptive system to make the generators less sensitive to process variations. The first structure allows us to generate high quality ramp signal. In a second step, a very high accuracy triangle-wave signal generator is presented in order to improve the equivalent linearity of the generated analog test signal.     

Extended Synchronous Dataflow for Efficient DSP System Prototyping

Though synchronous dataflow (SDF) graph has been a successful input specification language for digital signal processing (DSP) applications, lack of support for global states makes it unsuitable for multimedia signal processing applications that need global states for efficient implementation. In this paper, we propose synchronous piggybacked dataflow (SPDF), an extension of SDF model to accommodate global states without side effects. Global states are accessed by a special block that piggybacks the global state update request on data samples. Such an extension enlarges the domain of application where dataflow representation can be used for rapid system prototyping. The only penalty it incurs is scheduling complexity since the scheduler now considers control dependency as well as data dependency. We present the static analysis of the SPDF model and an implementation technique for memory efficient code synthesis. Finally, we show experimental results with a real life example, MPEG-audio decoder, to present the novelty and usefulness of our approach.     

Formal Verification of mCWQ Using Extended Hoare Logic

Mobile Networks and Applications - Node mobility, as one of the most important features of Wireless Sensor Networks (WSNs), may affect the reliability of communication links in the networks,...     

基于抽象解释的函数不变量正确性验证

函数不变量检测是提高软件质量的一种有效方法.针对检测方法可能带来无效的函数不变量的缺陷,提出一种以抽象解释理论为基础的函数不变量的正确性验证方法.首先将函数不变量转化成多项式关系;其次结合多项式程序与最弱前置条件抽象解释分析多项式关系正确性的判断依据;最后构造多项式关系算法,凭借得到的结果验证函数不变量正确与否.同时通过一个C程序中的函数不变量为例对该验证方法进行说明.     

功能覆盖率驱动的自适应遗传算法验证技术

根据不同功能测试点在芯片代码中的逻辑深度与相应测试向量覆盖到的测试点多少的关系,对不同测试点设置了相应的权重,提出一种基于自适应遗传算法的激励向量生成方法。实验结果表明,该方法能减少编写约束文件时间,较快自动搜索有针对性的测试激励,提高芯片功能验证的可靠性和仿真效率。     

下一代的模拟和射频设计验证工具

目前最先进的模拟和射频电路,正广泛应用于消费电子产品、无线通讯设备、计算机和网络设备的SoC中。它们带来了一系列验证方面的挑战,而这些挑战往往是传统SPICE、FastSPICE和射频仿真软件无法完全解决的。本文将探讨Berkeley设计自动化公司的精确电路分析工具如何能够帮助领先的半导体公司显著降低产品验证时间,从而迅速投入批量生产。     

一种嵌入式CPU功能验证平台的设计

功能验证是嵌入式CPU设计中一项复杂而重要的工作.针对某8位嵌入式CPU的设计要求,提出了一种嵌入式CPU的高度集成化的功能验证平台.该验证平台集成了整个功能验证流程,包括验证程序开发、验证程序调试、验证数据生成、验证Testbench、验证配置环境、覆盖率分析、结果比较和分析及基于FPGA的硬件验证平台等.验证平台通过代码覆盖率的分析来改善验证的完备性.该验证平台原理清晰,结构简单,扩展灵活,提高了功能验证的效率和自动程度,对其它CPU验证平台的设计具有一定的参考价值.     

Design of Efficient Generation Markets

The design of spot markets for generation services, such as energy, regulation,and operating reserves, and longer term markets for capacity, remain in evolution in many countries. Market design includes definition of the service, bid, or offer requirements, and rules for pricing and financial settlement. In the United States, most organized regional markets have converged on similar elements of spot market design. The design of capacity markets remains influx. Market power mitigation is currently a regulatory requirement in the United States, and experience with different methods shows that it must be carefully aligned with market design to ensure both efficient pricing and efficient investment. This paper surveys these topics and their relationships to each other and identifies researchable issues.     

A Framework for Seamless Roaming Across Heterogeneous Next Generation Wireless Networks

In the future, wireless and mobile users will have increased demands for seamless roaming across different types of wireless networks, quality of service guarantees and support of different types of services. This awareness has led to research activities directed towards inter-system and global roaming and can be noticed in the numerous products like multimode handsets, inter-working gateways and some ongoing standards and research work on signaling protocols for inter-system roaming. This article proposes a global mobility management framework. The framework is like an overlay network comprising of Inter-System Interface Control Units IICU to support inter-network communication and control for Location Management. The protocols and functions of this framework will be distributed and exist partly within the wireless networks and partly within the core-network. A hierarchy introduced among the IICUs will accommodate for the varying mobility coverage required by the mobile user. The IICU may be configured to perform various functions depending on its placement in the hierarchy of the framework. This approach aims to optimize across call set up delays, signaling traffic, database processing, handoff facilitation for seamless roaming and QoS mapping and negotiations as the user moves across different wireless networks. It avoids centralized database dependency with its associated single-point bottleneck and failures. We restrict our analysis of the framework to a 2-network and a 3-network roaming scenario. The presentation has been further restricted to cost and delay analysis of the location update and call delivery procedures. We have taken into account the signalling requirements when the mobile user roams across networks with and without an active call. Nirmala Shenoy is Associate Professor at the Information Technology department at RIT. She has several years of teaching and research experience while working in Germany, Singapore and Australia before she moved to USA. She is an avid researcher in the wireless networks area and has technically led several wireless network projects to success. She holds a Ph.D. in computer science from the University of Bremen, Germany, Masters in Applied Electronics and Bachelors in Electronics and Telecommunications Engineering both from Madras University in India. Professor Shenoy is interested in research in the area mobility management and modeling for wireless networks, Quality of service in wireless networks and the Internet.     

基于VMM统一验证平台的处理器芯片功能验证

本文结合处理器芯片实际项目,重点介绍了功能验证环节的工作。文章基于VMM验证平台,利用System Verilog语言自动生成测试激励,采用断言和功能覆盖率相结合的验证方法,实时监测RTL模型运行时的各种信号,自动进行覆盖率统计,通过增加约束实现覆盖率的快速收敛。文章最终给出了基于VMM验证平台进行功能验证的结果,绘制了功能覆盖率上升曲线。     

Functional Verification Based on FPGA for AVS Video Decoder

In this paper,based on the field-programmable gate array(FPGA)xc5vlx220 of Xilinx Company,the FPGA verification method for application specific integrated circuit(ASIC)design is introduced.Firstly,the basic principles of FPGA verification are introduced.Then,the structure of the FPGA board and the verification methods are illustrated.Finally,the workflow of FPGA verification for audio video coding standard(AVS)decoder and the method of restoring images are introduced in detail.The FPGA resources occupancy i...     

Efficient Path Delay Test Generation for Custom Designs

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.     

最新高效率光伏逆变器拓扑结构及功率器件介绍

效率正成为电力电子装置设计中越来越重要的参数。在某些应用中,效率甚至成为行业发展的驱动力,典型的如太阳能发电行业。因为对于光伏发电行业,效率的提升可以直接带来经济效益。本文详细介绍了最新的能够提供高效率的光伏逆变器拓扑结构和功率器件,包括单相和三相逆变器,功率因数补偿对策,高效电流双向流动逆变器等。