一种CMOS双沿触发器的设计

基于CMOS传输门,分析了单、双沿触发器的逻辑结构,分析了一种晶体管数较少的CMOS双沿触发器,并用PSPICE程序进行了模拟,结果表明这种双沿触发器具有完整的逻辑功能,且具有结构简单,延迟时间短和数据处理能力高的优点,另外,与传统的单沿触发器相比,其功耗大约减少了61%。     

Analysis of mesastable operation in RS CMOS flip-flops

An analysis of metastable operation in CMOS RS flip-flops is presented. An analytical formula for the flip-flop resolving time constant was derived using Shichman-Hodges model for NMOS and PMOS transistors. This formula, as related to the transistor dimensions, fabrication process parameters, and parasitic capacitance, uses proper transistor sizing to attain minimum flip-flop failure rate due to metastable operation. CMOS n-well, p-well, and twin-well flip-flop performance predicted analytically is also approved by SPICE level one simulation of transistor models. Real-time oscilloscope displays of metastable operation for two different CMOS RS flip-flop circuits are demonstrated.     

Aging comparative analysis of high-performance FinFET and CMOS flip-flops

This paper presents a comparative performance analysis to investigate the impact of aging mechanisms on various flip-flops in CMOS and FinFET technologies. We consider Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) effects on the robustness of high performance flip-flops. To apply BTI and HCI aging mechanisms, we utilize long-term model to estimate ∆ V_th and employ the updated V_th in transistor model file. The simulation results on performance analysis indicate the high ranking of various flip-flops considering speed and power consumption in each CMOS and FinFET technologies, moreover, approve the superiority of static FinFET flip-flops over CMOS flip-flops. In addition, a comparative analysis considering temperature and V_DD variations over different FinFET flip-flop structures demonstrates the average percentages of T_DQmin and PDP degradation against aging mechanisms are significantly less than similar CMOS flip-flops.     

Metastability behavior of CMOS ASIC flip-flops in theory and test

Basic flip-flop structures are compared with the main emphasis on CMOS ASIC implementations. Flip-flop properties are analyzed by means of simplified models, some structural approaches for optimized metastable behavior are discussed. A special integrated test circuit which facilitates accurate and reproducible measurements is presented. The circuit has been used for carrying out metastability measurements in a wide temperature and voltage range to predict circuit parameters for worst-case designs. Results from measurements and circuit simulation indicate that different criteria for optimizing flip-flop performance should be used for synchronizers and for those applications where the observation of timing constraints imposed on flip-flop input signals can be guaranteed. These results can help in determining the reliability of existing synchronizer and arbiter designs. By means of special synchronizer cells the reliability of asynchronous interfaces can be improved significantly, enabling the system design to gain speed and flexibility in communication between independently clocked submodules     

A novel CMOS multivibrator

The paper describes a CMOS multivibrator using a differential pair with positive feedback via a current mirror and a diode-connected NMOS transistor; the output voltage is taken at this transistor. The timing capacitor is charged by a current source and discharged by the differential pair tail current. During capacitor charging the tail current is steered into the current mirror. The mirror output current is applied to a diode-connected transistor and creates the HIGH level of the output voltage. During discharging the diode connected transistor obtains a small current (from another current source) which determines the LOW level of the output voltage. The capacitive loading and frequency limit are investigated. The design procedure is given. The body effect does not affect the circuit performance. This allows to reduce the multivibrator area.     

TWO-INPUT PRESETTING TECHNIQUE AND DESIGN OF CMOS FLIP-FLOPS WITH A HIGH RADIX

By analysing the difficulty of previous flip-flops with a high radix, this paper proposes a logic design scheme with two presetting inputs. The circuit of a quaternary CMOS flip-flop is designed by using the transmission function theory. The result shows that its structure is simpler and its processing speed is higher than that of two binary flip-flops which store the equal information.     

A circuit implementation of a single-bit CMOS adder

In this article, a circuit implementation of a single-bit CMOS adder with enhanced performance is presented. The adder circuit consists of separate circuits operating in-parallel for obtaining the output sum and carry signals. The carry circuit signal is not used to form the sum signal. The sum signal circuit is a sequential connection of two XOR cells. The circuit operability is confirmed by the results of circuit simulation using Cadence Design Systems’ software.     

一种新颖全差分光电集成接收机的标准CMOS实现

提出一种新颖的全差分光电集成接收机,它包含了全差分光电探测器和相应的差分接收电路,其中全差分光电探测器的作用是实现入射光信号到全差分光生电流信号的转换.采用特许3.3 V、0.35μm标准CMOS工艺,实现了一种相应的宽带、高灵敏度全差分光电集成接收机.测试结果表明:对于850 nm的入射光,集成全差分光电探测器的差分跨阻前置放大器(TIA)的工作速率可达到500 Mbit/s,而整个光接收机的带宽则达到了1.098 5 GHz;在10-12的误码率条件下,灵敏度可达到-12.3 dBm.     

Min-net winner-take-all CMOS implementation

A charge-based winner-take-all (WTA) circuit is proposed. This WTA circuit is a min-net capable of selecting the minimum value among its input nodes and gives only one low voltage for the corresponding output node. The charge-based circuit uses a power supply of 3 V, with low power dissipation due to the lack of static DC current involved. The WTA circuit is used in associative neural networks.<>     

A novel open-loop high-speed CMOS sample-and-hold

A new open-loop high-speed CMOS sample-and-hold is presented. Based on new method for further reduction of voltage-dependent charge injection, a new CMOS sample-and-hold was designed. Simulation results confirm the effectiveness of this method. Over 10 dB improvement in signal-to-noise ratio, compared to the signal-to-noise ratio of conventional bottom plate sampling S/Hs was achieved with this method. A comparison between newly designed S/H and the bottom-plate sampling S/H is presented.     

Neuro-fuzzy architecture for CMOS implementation

In this paper, a nonconventional structure for a “fuzzy” controller is proposed. It does not require signal division, and it produces control surfaces similar to classical fuzzy controllers. The structure combines fuzzification, MIN operators, normalization, and weighted sum blocks. The fuzzy architecture is implemented as a VLSI chip using 2-μm n-well technology. A new fuzzification circuit, which requires only one differential pair per membership function is proposed. Eight equally spaced membership functions are used in the VLSI implementation. Simple voltage MIN circuits are used for rule selection. A modified Takagi-Sugeno approach with normalization and weighted sum is used in the defuzzification circuit. Weights in the defuzzifier are digitally programmable with 6-bits resolution     

一种新颖的高可靠CMOS SRAM 单元

本文提出了一种新颖的8管抗SUE,高噪声容限的SRAM单元。通过在每个访问晶体管上增加了一个并联的晶体管,上拉PMOS的驱动能力可以设计的比传统单元的PMOS的驱动能力更强,读访问晶体管可以设计得比传统单元的读访问晶体管更弱。因此保持,读噪声容限和临界电荷都有较大提高。仿真结果表明,与传统的6管单元相比,合理设计上拉晶体管尺寸后,临界电荷提高了将近3倍。保持和读静态噪声容限分别提高了72%和141.7%。但该新式单元的面积额外开销为54%,读性能也有所下降,适用于高可靠性应用,如航天,军事等。     

A novel high reliability CMOS SRAM cell

A novel 8T single-event-upset(SEU) hardened and high static noise margin(SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor,the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell.So the hold,read SNM and critical charge increase greatly.The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors.The hold and read SNM of the new cell increase by 72%and 141.7%,respectively,compared to the 6T design,but it has a 54%area overhead and read performance penalty.According to these features,this novel cell suits high reliability applications,such as aerospace and military.     

一种新的CMOS MOCCII的高频补偿方法

本文提出了一种简单而有效的具有高频补偿的CMOS MOCCII电路.对于电压传输函数V_X/V_Y,采用源极电容耦合放大器的方式实现高频补偿;对于电流传输函数I_z/I_x、I_(z-)/I_x,采用在电流镜中加一个可调电阻方法,使得电流镜的传输函数由一阶系统变成可调极点的二阶系统,调节电阻大小,使得极点远离S平面原点,从而提高电流镜频带宽度.仿真表明,V_X/V_Y的转折频率由补偿前的92.690MHz提高到补偿后的184.127MHz;I_z/I_x及I_(z-)/I_x的转折频率分别由补偿前的66.708MHz、58.780MHz提高到补偿后的272.965MHz和279.042MHz,而-3dB截止频率分别达到871.936MHz和814.185MHz.最后,从应用方面给出了由补偿前后MOCCII所构成的电流模式滤波器.     

A synchronous switched capacitor filter [CMOS Si-gate implementation]

A new switched capacitor circuit is presented, realizing a moderate to high Q frequency emphasizing network. The original feature of this circuit is that its resonant frequency is equal to one half of the sampling frequency, and independent of the accuracy of the capacitor ratio or of any imperfection, both affecting only the Q factor. The gain is nearly proportional to the Q factor. An experimental circuit has been implemented in CMOS Si-gate technology with a programmable gain of 20 dB and 40 dB, corresponding to a Q factor of 8.6 and 79, respectively. Experimental results are in good agreement with the theory. Modifications of the basic circuit are proposed to cancel the effects of parasitic capacitances and to reduce the chip area.     

Low-voltage fourth-order CMOS sigma-delta modulator implementation

A low-voltage, high-speed, fourth-order sigma-delta modulator implementation is presented. The low-voltage and high-speed operation are obtained by using a novel combination of architectural features, proper circuit structure selections, specific clocking strategies, and efficient circuit optimisation algorithms. Measurement results from fabricated CMOS chip prototypes show a good match with simulations     

一种新型的CMOS集成湿度传感器

利用MEMS技术 ,对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造 ,采用梳状铝电极结构、梳状多晶硅加热结构 ,衬底接地 ,感湿介质采用聚酰亚胺 ,利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路 ,输出可测电压信号 ,利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系     

A novel CMOS hairpin resonator using slow-wave structure

A novel hairpin resonator incorporating a defective uniplanar compact photonic bandgap (D-UCPBG) slow-wave structure has been developed using monolithic silicon-based CMOS technology and the impact of the D-UCPBG slow wave feature on the hairpin resonator performance is presented. Two stepped impedance hairpin resonators of equal dimensions, one with a solid ground plane and another with a D-UCPBG structure, were implemented in the TSMC 0.25 /spl mu/m RF-mixed signal fabrication process. The D-UCPBG incorporated hairpin resonator resonates at 4.5 GHz, a significant frequency reduction from 10.2 GHz, the resonant frequency of the solid ground plane based hairpin resonator. The loaded Q of the resonator also increases from 5.8 for the solid ground plane resonator to 13 for the D-UCPBG structure.     

一种新型的CMOS集成湿度传感器

利用MEMS技术，对一种新型CMOS湿度传感器进行理论分析、模拟以及结果讨论。该湿度传感器采用标准CMOS工艺制造，采用梳状铝电极结构、梳状多晶硅加热结构，衬底接地，感湿介质采用聚酰亚胺，利用商业软件Coventor进行模拟绘制出敏感电容与相对湿度的曲线图。接口电路采用开关电容电路，输出可测电压信号，利用Microsim公司的Pspice模拟电路得到相对湿度与输出电压曲线关系。