An NMOS input merged bipolar/sidewall-MOS transistor with a bypasssidewall MOS transistor (NBiBMOS transistor)

The concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (V_CE or V_DE) is less than the turn-on voltage of the n-p-n bipolar transistor (V_BE=~0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and DC characterizing the NBiBMOS transistor structures, which occupy ~1.2 times the area of a single n-p-n bipolar transistor. The NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor, because the body-source junction of the bypass NMOS transistor is forward biased     

High frequency performance of SiC heterojunction bipolartransistors

A compact heterojunction bipolar transistor (HBT) model was employed to simulate the high frequency and high power performances of SiC-based bipolar transistors. Potential 6H-SiC/3C-SiC heterojunction bipolar transistors (6H/3C-HBT's) at case temperatures of 27°C (300 K) through 600°C (873 K) were investigated. The high frequency and high power performance was compared to AlGaAs/GaAs HBT's. As expected, the ohmic contact resistance limits the high frequency performance of the SiC HBT. At the present time, it is only possible to reliably produce 1×10^-4 Ω-cm² contact resistances on SiC, so an f_T of 4.4 GHz and an f_max of 3.2 GHz are the highest realistic values. However, assuming an incredibly low 1×10^-6 Ω-cm² contact resistance for the emitter, base, and collector terminals, an f_T of 31.1 GHz and an f_max of 12.7 GHz can be obtained for a 6H/3C-SiC HBT     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

Vertical bipolar transistors fabricated in local silicon oninsulator films prepared using confined lateral selective epitaxialgrowth (CLSEG)

A new technique called the confined lateral selective epitaxial growth (CLSEG) process has been used successfully to produce thin local silicon-on-insulator (SOI) films of high material quality. Two different vertical bipolar transistor structures are fabricated in local SOI to evaluate the material quality and to demonstrate the versatility of the CLSEG technique. The first bipolar structure emitter is formed by ion implantation silicon and demonstrates maximum DC current gains (β _max) of 400 with junction ideality factors of less than 1.08. A second bipolar structure is fabricated which simultaneously forms both the emitter and subcollector regions. The subcollector is formed on the underside of the local SOI film by exposing it during the emitter phosphorus diffusion and serves to reduce parasitic collector resistance (r'_C). These nonoptimized underdiffused devices have measured β_max=158 and lower r'_C. A PISCES simulation accurately predicts the measured r'_C value and indicates values at least as low as 74 Ω in an optimized layout     

High speed submicron BiCMOS memory

This paper reviews device and circuit technologies for submicron BiCMOS memories, especially for high speed and large capacity SRAM's with 0.8 μm, 0.55 μm and 0.4 μm design rules. First, poly-silicon emitter structure and triple-well structure are described as key submicron BiCMOS device technologies for achieving high transistor performance and minimized process complexity, as well as high reliability. Next, submicron CMOS and BiCMOS inverter gate delays are compared. In addition, memory circuit techniques including BinMOS logic gates and bipolar sense amplifiers are discussed, respectively for ECL I/O asynchronous, TTL I/O asynchronous and super high speed synchronous submicron BiCMOS SRAM's. Future prospects for submicron BiCMOS memories are also forecasted     

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-MbDRAM's

A 0.3-μm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V_cc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; (3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and (4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed DRAMs, based on the 4-Mb design     

A BiCMOS technology with 660-MHz vertical p-n-p transistor foranalog/digital ASICs

A fully complementary BiCMOS technology based on a 2-μm process designed for 12-V analog/digital applications is described. In this technology, a triple diffused vertical p-n-p transistor and n-p-n bipolar and CMOS devices are integrated in a single chip. A transition frequency of 660 MHz and a collector-to-emitter breakdown voltage of over 15 V have been obtained for the collector-isolated p-n-p transistor by adding only one extra mask to a conventional 2-μm BiCMOS process. The total number of masks is 20 with double-layer metallization. A unity gain frequency of 52 MHz and a DC gain of 85 dB have been obtained for a single-supply operational amplifier with a vertical p-n-p first stage. The propagation delay time for a CMOS two-NAND gate was 1.27 ns driving three loads and 3 mm of metal     

Substrate coupling evaluation in BiCMOS technology

The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of Rc make the transistor less noisy. A test chip is fabricated in 3-μm BiCMOS technology to measure the substrate coupling produced by different BICMOS inverter gates. These experimental measurements show that noise increases with transistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible     

Extremely high peak specific transconductance AlGaAs/GaAsheterojunction bipolar transistors

Self-aligned AlGaAs/GAs heterojunction bipolar transistors with peak specific transconductances as high as 25 mS/μm² of emitter area are discussed. These are the highest specific transconductances ever reported for a bipolar transistor. These devices, which contain no indium in the emitter, display specific parasitic emitter resistances of less than 1×10^-7 Ω-cm². This low parasitic resistance is attributed to an improved n-type contact technology, in which a molybdenum diffusion barrier and a plasma-enhanced chemical vapor deposition SiO₂ overlayer are used to achieve low specific contact resistivities     

Extraction method of the base series resistances in bipolartransistor in presence of current crowding

This paper proposes a new method to determine the base resistance components and the base sheet resistance under forward bias conditions and in the presence of current crowding. Using bipolar transistors with two independent base contacts, the base sheet resistance R_□ and the extrinsic resistance component R_Bx are first extracted. Accounting for current crowding, the total base resistance is subsequently calculated using an analytical analysis of the debiasing effects. The assessment of this method is accomplished by exercising the algorithm with current/voltage data generated by two dimensional numerical simulations. The simulated structure corresponds to an advanced npn transistor embedded in the QUBiC BiCMOS technology. The extracted quantities are directly compared to their strictly integrated counterparts determined from the internal current and voltage distributions     

A high-current-gain low-temperature pseudo-HBT utilizing a sidewallbase-contact structure (SICOS)

A silicon pseudo-heterojunction bipolar transistor (HBT) with a current gain of over 100 at 77 K has been successfully fabricated using the upward operation of a self-aligned sidewall base-contact structure (SICOS). The measured characteristics agree well with the theoretical prediction, showing a negative exponential temperature dependence of current gain and a 2500-times larger collector current than in the conventional transistor at 77 K. This makes homojunction bipolar transistor operation at low temperatures feasible and has the potential to overcome the bipolar/BiCMOS limitations     

Schottky merged BiCMOS structures

A new merged BiCMOS structure is presented. It incorporates a Schottky diode between the base and the collector of the n-p-n bipolar transistor. The structure offers the same reduced area advantage of merged over conventional BiCMOS, and is shown to have granted latchup immunity to BiCMOS circuits. The device simulations using HSPICE verify the latchup immunity     

High-speed BiCMOS technology with a buried twin well structure

A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (fT= 4 GHz) and small size (500 µm²) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.     

A BiCMOS thermal head intelligent driver with density controllersfor full-tone rendition printers

A 3-μm BiCMOS thermal head driver using pulsewidth modulation dealing with eight-bit density input data (256 gray levels) is described. Circuits composed of 64×8-bit complex counters, which function as eight-line parallel 64-bit shift registers (shift mode) and as 64 counters which have eight bits (count mode) by alteration of their mutual connections according to the mode signals, have been developed. The complex counter controls the output pulse width according to the binary data and the clock intervals (minimum 100 ns). The shift registers can operate using a 20-MHz clock. The driver consists of about 4500 CMOS gates and 128 bipolar transistors in a 2.8-mm×8.8-mm chip size. The breakdown voltage of the bipolar transistor BV _cbo is more than 35 V. The driver is especially suited for full-tone rendition printers. Applications of the driver include use in thermal print heads, LED print heads, and LCD print heads     

A new simultaneous noise and input power matching technique formonolithic LNA's using cascode feedback

In this paper, a new simultaneous impedance-matching technique of Γ_opt (optimum noise-match source reflection coefficient) and G_max (maximum available power gain-match (MAPG) source reflection coefficient) using cascode feedback (CF) is proposed. A 1.57-GHz single-stage monolithic-microwave Integrated-circuit (MMIC) low-noise amplifier (LNA) designed with this technique has been fabricated using GaAs MESFET technology in order to verify the feasibility of this scheme. The measured response agrees well with the simulated performance. Extensive computer simulation shows that when silicon npn bipolar junction transistor (BJT) is used, this scheme enables us to make both Γ_opt and G_max points near to 50 Ω, in addition to the simultaneous noise and input power matching. In addition, it has all the advantages of negative feedback such as stability, wider bandwidth, and insensitivity against parameter variation     

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

This paper proposes a novel low-leakage BiCMOS deep-trench (DT) diode in a 0.18-/spl mu/m silicon germanium (SiGe) BiCMOS process. By means of the DT and an n/sup +/ buried layer in the SiGe BiCMOS process, a parasitic vertical p-n-p bipolar transistor with an open-base configuration is formed in the BiCMOS DT diode. Based on the two-dimensional (2-D) simulation and measured results, the BiCMOS DT diode indeed has the lowest substrate leakage current as compared to the conventional p/sup +//n-well diode even at high temperature conditions, which mainly results from the existence of the parasitic open-base bipolar transistor. Considering the applications of the diode string in electrostatic discharge (ESD) protection circuit designs, the BiCMOS DT diode string also provides a good ESD performance. Owing to the characteristics of the low leakage current and high ESD robustness, it is very convenient for circuit designers to use the BiCMOS DT diode string in their IC designs.     

An experimental 1-Mbit BiCMOS DRAM

Three developments are proposed for high-performance DRAMs: a bipolar complementary MOS (BiCMOS) DRAM device structure featuring high soft-error immunity due to a p/SUP +/ buried layer; a high-speed circuit configuration of eight NMOS subarrays combined with BiCMOS peripheral drivers and BiCMOS data output circuitry; and BiCMOS voltage and current limiters lowering power dissipation as well as peak current. A 1.3 /spl mu/m 1-Mb DRAM is designed and fabricated to verify the usefulness of these BiCMOS DRAM technologies. Features of this chip include a typical access time of 32 ns, a typical power dissipation of 450 mW at a 60-ns cycle time, and chip size of 5.0/spl times/14.9 mm/SUP 2/.     

Nonoverlapping super self-aligned device structure forhigh-performance VLSI

The nonoverlapping super self-aligned structure (NOVA) is reported. Because of its nonoverlapping nature, this structure can be applied equally well to bipolar, CMOS, or BiCMOS processes. This structure effectively minimizes parasitic capacitance and resistance for both the MOS and bipolar devices. CMOS and bipolar devices are integrated into a high-performance BiCMOS technology. CMOS and emitter-coupled logic (ECL) ring oscillators with 1.5-μm lithography are reported to have delays of 128 and 87 ps/stage, respectively     

Device characteristics of the GaAs/InGaAsN/GaAs p-n-p doubleheterojunction bipolar transistor

We have demonstrated the dc and rf characteristics of a novel p-n-p GaAs/InGaAsN/GaAs double heterojunction bipolar transistor. This device has near ideal current-voltage (I-V) characteristics with a current gain greater than 45. The smaller bandgap energy of the InGaAsN base has led to a device turn-on voltage that is 0.27 V lower than in a comparable p-n-p AlGaAs/GaAs heterojunction bipolar transistor. This device has shown f_T and f_MAX values of 12 GHz. In addition, the aluminum-free emitter structure eliminates issues typically associated with AlGaAs