Metastability of SOI CMOS latches

An analysis of the metastability of silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) latches is presented, using partially-depleted SOI devices with various body-connection topologies and an unbuffered latch. The metastability window, resolution time and time interval between the clock edge and the time t _meta are evaluated as functions of power supply and the type of body-connection topology. Simulations using SOISPICE show improved metastability behaviour for SOI specific body-connection topologies.     

Power-efficient metastability error reduction in CMOS flash A/Dconverters

A power and area efficient technique to reduce metastability errors in high-speed flash A/D converters is described. Pipelining to reduce error rates in an n-bit flash converter is accomplished with a bit pipeline scheme requiring n latches per pipeline stage instead of 2 ⁿ-1. A 7-b, 80 MHz prototype converter is implemented in 1.2-μm CMOS with measured metastability error rates of less than 10 ^-12 errors/cycle. The measured power is 307.2 mW with an 80-MHz sampling frequency. Without metastability error reduction circuitry, the estimated metastability error rate for the converter is 10^-4 errors/cycle. Achieving an equivalent error rate with two pipeline stages of 2ⁿ-1 latches would require 3.48 times the power for the metastability error reduction circuitry. This corresponds to a reduction in total power by a factor of 1.24 compared with the comparator pipelined converter for Nyquist frequency inputs     

Metastability and relaxation processes in hydrogenated amorphous silicon

The kinetics of structural relaxation in hydrogenated amorphous silicon (a-Si:H) deposited by various methods is investigated by differential scanning calorimetry. The experimental results are used to analyze the nature of the metastable states in a-Si:H and to investigate the relationship between structural relaxation and light-induced metastability (the Staebler-Wronski effect). Fiz. Tekh. Poluprovodn. 31, 1449–1454 (December 1997)     

Burst error generator using flip-flop metastability

A novel burst error generator for communications systems testing is presented which is based on the phenomenon of metastability observed in flip-flops. Bursts can be created with predetermined bit error ratios by means of an external control voltage. The errors appear to follow a double Poisson distribution, characteristic of the Neyman type A contagious process     

Metastability tests of flip-flops in programmable digital circuits

This paper describes the methods and experimental techniques for determination of the metastability behavior of the flip-flops used in the programmable digital circuits. A dual model of the metastability distinguishes two transitions at the flip-flop output (L/H and H/L) which have different impact on the Mean Time Between Failures (MTBF) of the flip-flop. A new circuit of the late transition detector (LTD) allows for determination of the pairs of the metastability parameters, the window W and the time constant τ, for both transitions. The test results are presented for four types of programmable digital circuits fabricated commercially in CMOS technology. In the all tests, the H/L transition clearly dominates with respect to MTBF (as a worse one). The presented test methods can also be used for evaluation of flip-flops in nonprogrammable digital circuits.     

Supply noise and CMOS synchronization errors

The effects of supply disturbances on synchronization failures in CMOS latches are examined. In contrast to prior work, supply noise is shown to increase a synchronizer's metastability error rate. Buffering the synchronizer to reduce these errors is shown to have little effect on the noise immunity. Measured results are presented from a test setup with a 2-μm CMOS test chip to verify the findings     

Heat‐Free Fabrication of Metallic Interconnects for Flexible/Wearable Devices

Exploiting interfacial excess (Γ), Laplace pressure jump (ΔP), surface work, and coupling them to surface reactivity have led to the synthesis of undercooled metal particles. Metastability is maintained by a core–shell particle architecture. Fracture of the thin shell leads to solidification with concomitant sintering. Applying Scherer's constitutive model for load‐driven viscous sintering on the undercooled particles implies that they can form conductive traces. Combining metastability to eliminate heat and robustness of viscous sintering, an array of conductive metallic traces can be prepared, leading to plethora of devices on various flexible and/or heat sensitive substrates. Besides mechanical sintering, chemical sintering can be performed, which negates the need of either heat or load. In the latter, connectivity is hypothesized to occur via a Frenkel's theory of sintering type mechanism. This work reports heat‐free, ambient fabrication of metallic conductive interconnects and traces on all types of substrates.     

高速CMOS闪烁型模数转换器中的误差源研究

对高速CMOS闪烁型模数转换器中的六种误差源进行了研究.每个误差源会潜在的限制模数转换器的线性度和信噪比.这些误差源包括基准电压的非理想因素、前置放大器引入的输入有关的时间延迟、比较器的回程噪声、时钟抖动与分布特性、温度计码中的火花码、比较器的亚稳态.在每种误差源研究的基础上,给出了相应的电路解决技术,使得吉赫频率范围中等分辨率的CMOS闪烁型ADC成为现实.     

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance

A 65 nm resilient circuit test-chip is implemented with timing-error detection and recovery circuits to eliminate the clock frequency guardband from dynamic supply voltage (V_CC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. One EDS circuit is a dynamic transition detector with a time-borrowing datapath latch (TDTB). The other EDS circuit is a double-sampling static design with a time-borrowing datapath latch (DSTB). In comparison to previous EDS designs, TDTB and DSTB redirect the highly complex metastability problem from both the datapath and error path to only the error path, enabling a drastic simplification in managing metastability. From a survey of various EDS circuit options, TDTB represents the lowest clock energy EDS circuit known; DSTB represents the lowest clock energy static-EDS circuit with SER protection known. Error-recovery circuits are introduced to replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, test-chip measurements demonstrate that resilient circuits enable either 25%-32% throughput gain at equal V_CC or at least 17% V_CC reduction at equal throughput, corresponding to 31%-37% total power reduction.     

Linear‐Time Korean Morphological Analysis Using an Action‐based Local Monotonic Attention Mechanism

For Korean language processing, morphological analysis is a critical component that requires extensive work. This morphological analysis can be conducted in an end‐to‐end manner without requiring a complicated feature design using a sequence‐to‐sequence model. However, the sequence‐to‐sequence model has a time complexity of O(n²) for an input length n when using the attention mechanism technique for high performance. In this study, we propose a linear‐time Korean morphological analysis model using a local monotonic attention mechanism relying on monotonic alignment, which is a characteristic of Korean morphological analysis. The proposed model indicates an extreme improvement in a single threaded environment and a high morphometric F1‐measure even for a hard attention model with the elimination of the attention mechanism formula.     

Synchronization reliability in CMOS technology

The synchronization performance of CMOS circuits is examined theoretically and experimentally. Criteria for maximizing CMOS gain are determined and are then compared with NMOS gain curves. The phase characteristics of metastability are identified. Experimental measurements of error rate are made on a CMOS test circuit, and the gain-bandwidth product for the circuit is determined from these data.     

Use of data permutation to reduce the peak‐to‐average power ratio of an OFDM signal

A set of fixed permutations is used in this paper to reduce the peak‐to‐average power ratio (PAR) of an orthogonal frequency division multiplexing (OFDM) signal. For this technique, K − 1 interleavers are used to produce K − 1 permuted sequences from the same information sequence. The peak powers of the permuted sequences and the original information sequence are computed using K inverse discrete Fourier transforms; the sequence with the lowest PAR is chosen for transmission. Before the optimization process begins the identity of each interleaver is embedded into the data frame as side information (SI). SI which is critical to the receiver operation, is coded using a simple forward error correction code in order to increase its reliability. An adaptive approach is proposed for the reduction of this technique's complexity. Furthermore, theoretical expressions are derived for the complementary cumulative distribution function of the PAR and for the average number of permutations required by the adaptive approach. Computer simulations are performed for finding the PAR reduction capability of several types of interleavers. It is subsequently found that random interleavers and odd–even symmetric interleavers are performing equally well in reducing the PAR. Results are also presented for the out of band radiation and the bit error rate performance of interleaved OFDM (IOFDM) and conventional OFDM in an additive white Gaussian noise channel. IOFDM also has less adjacent channel interference than that of conventional OFDM. Copyright © 2002 John Wiley & Sons, Ltd.     

Accurate series resistance measurement of solar cells

The series resistance (R_s) of a solar cell is commonly represented as a constant resistance value. However, because of the distributed nature of series resistance, the effective lumped R_s vary with current density and illumination intensity. Treating R_s as a constant is usually insufficient for an accurate analysis of its J–V curve. This work first presents a review of the distributed nature of series resistance and commonly applied methods to measure R_s. Particular attention is given to the multi‐light method (MLM) and it is discussed in detail, where R_s in both the light and dark can be measured as a function of current by extracting R_s from a set of current–voltage (J–V) curves attained at different illumination intensities. The principle behind this method is discussed, and the results are then compared with those of other known methods of R_s measurement. The accurate measurement of R_s(J) attained with the MLM permits the extraction of an R_s‐corrected J–V curve, which is theoretically more accurate than that attained by alternative methods because of negligible error from injection dependence and spectral mismatch. With the solar cell equation modified to include R_s(J), we attain a much better fit to experimental data, finding a significant reduction in error compared with using a constant R_s. Copyright © 2011 John Wiley & Sons, Ltd.     

New challenges to the modelling and electrical characterisation of ohmic contacts for ULSI devices

Continuing developments in semiconductor process and materials technology have enabled significant reductions to be achieved in the contact resistance R_c of devices. This reduction is commonly assessed in terms of the specific contact resistance (SCR) parameter ρ_c (Ω cm²) of the metal–semiconductor interface. Such a reduction in SCR is essential, for as device dimensions decrease, then so also must ρ_c and the corresponding contact resistance in order not to compromise the down-scaled ULSI device performance. Thus the ability to accurately model contacts and measure ρ_c is essential to ohmic contact development. The cross kelvin resistor (CKR) test structure is commonly used to experimentally measure the Kelvin resistance of an ohmic contact and obtain the specific contact resistance ρ_c. The error correction curves generated from computer modelling of the CKR test structure are used to compensate for the semiconductor parasitic resistance, thus giving the SCR value. In this paper the increased difficulty in measuring lower ρ_c values, due to trends in technology, is discussed. The challenges presented by the presence of two interfaces in silicided contacts (metal-silicide–silicon) is also discussed. Experimental values of the SCR of an aluminium–titanium silicide interface is determined using multiple CKR test structures.     

Variable Step-Size Constant Modulus Algorithm Employing Fuzzy Logic Controller

The Constant Modulus Algorithm (CMA), although it is the most commonly used blind equalization technique, converges very slowly. The convergence rate of the CMA is quite sensitive to the adjustment of the step size parameter used in the update equation as in the Least Mean Squares (LMS) algorithm. A novel approach in adjusting the step size of the CMA using the fuzzy logic based outer loop controller is presented in this paper. Inspired by successful works on the variable step size LMS algorithms, this work considers designing a training trajectory that it overcomes hurdles of an adaptive blind training via controlling the level of error power (LOEP) and trend of error power (TOEP) and then obtains a more robust training process for the simple CMA algorithm. The controller design involves with optimization of training speed and convergence rate using experience based linguistic rules that are generated as a part of FLC. The obtained results are compared with well-known versions of CMA; Conventional CMA, Normalized-CMA [Jones, IEEE conference record of the twenty-ninth asilomar conference on signals, systems and computers (Vol. 1, pp. 694–697), 1996], Modified-CMA [Chahed, et al., Canadian conference on electrical and computer engineering (Vol. 4, pp. 2111–2114), 2004], Soft Decision Directed-CMA (Chen, IEE Proceedings of Visual Image Signal Processing, 150, 312–320, 2003) for performance measure and validation.     

Approximating a set of points by a step function

Let S be a set of n points in the plane. We derive algorithms for approximating S by a step function of size k < n, i.e., by an x-monotone rectilinear polyline with k < n horizontal segments. We use the vertical distance to measure the quality of the approximation, i.e., the maximum distance from a point in S to the horizontal segment directly above or below it. We consider two types of problems: min-ε, where the goal is to minimize the error for a given number of horizontal segments k and min-#, where the goal is to minimize the number of segments for a given allowed error ε. After O (n) preprocessing time, we solve instances of the latter in O (min{k log n, n}) time per instance. We can then solve the former problem in O (min{n², nk log n}) time. Both algorithms require O (n) space. Our second contribution is an approximation algorithm for the min-ε problem that computes a solution within a factor of 3 of the optimal error for k segments, or with at most the same error as the k-optimal but using 2k − 1 segments. Furthermore, experiments on real data show even better results than what is guaranteed by the theoretical bounds. Both approximations run in O (n log n) time and O (n) space.     

Peak‐to‐Average Power Ratio Reduction Using N‐tuple Selective Mapping Method for MC‐CDMA

The multi‐carrier transmission signal in Multi‐Carrier Code Division Multiple Access (MC‐CDMA) has a high peak‐to‐average power ratio (PAPR), which results in nonlinear distortion and deteriorative system performance. An n‐tuple selective mapping method is proposed to reduce the PAPR, in this paper. This method generates 2ⁿ sequences of an original data sequence by adding n‐tuple of n PAPR control bits to it followed by an interleaver and error‐control code (ECC) to reduce its PAPR. The convolutional, Golay, and Hamming codes are used as ECCs in the proposed scheme. The proposed method uses different numbers of the n PAPR control bits to accomplish a noteworthy PAPR reduction and also avoids the need for a side‐information transmission. The simulation results authenticate the effectiveness of the proposed method.     

Symbol error probability evaluation for PSK modulation schemes in generalized non‐Gaussian noise channels

The average symbol error probability (ASEP) performance over the faded radio frequency (RF) link when the noise is additive in nature and has generalized Laplacian distribution is evaluated in this paper. The additive white generalized Laplacian noise (AWGLN) distribution can model different impulsive and non‐Gaussian noise environments often encountered in practice and provides a robust alternative to Gaussian distribution. A new expression for evaluating the exact symbol error probability over a multilevel M‐ary PSK‐modulated AWGLN channel is derived. Based on the obtained expression, the ASEP for the single‐hop RF link that models the shadowing and fading conditions over the RF channel by a generalized –K (GK) distribution is derived. Further, the error performance of a decode‐and‐forward relayed and GK‐distributed two‐hop RF link is discussed, and the results are validated through numerical plots.     

Estimation of the error performance objectives for satellite communication systems

We consider the physical layer error performance parameters and design criteria for digital satellite systems established by ITU‐R Recommendation S.1062, where the performance objectives are given in terms of the bit error rate (BER) divided by the average number of errors within a cluster. It is well known that errors on satellite links employing forward error correction (FEC) schemes tend to occur in clusters. The resulting block error rate is the same as if it was caused by randomly occurring bit errors with an error‐event ratio of BER/α, where α is the average number of errors within a cluster. The factor, α, accounts for the burstiness of the errors and also represents the ratio between the BER and the error‐event ratio. This paper proposes theoretical methods to estimate the factor, α. Using the weight distributions of the FEC codes, we derive a set of expressions for the factor, α, as well as their compact lower bounds. We present lower bounds for various FEC schemes including binary BCH codes, block turbo codes, convolutional codes, and turbo codes. The simulation results show that the proposed lower bounds are good estimates in the high signal‐to‐noise ratio region. Copyright © 2008 John Wiley & Sons, Ltd.     

微粒粒度分布FD测量法的改进

基于Fraunhofer-Diffraction原理测量粒度分布的方法应用已久,然而,在实际应用中由于SSPD等光电器件性能的限制和反演中数学近似的误差影响了测量效果。对此,充分讨论了衍射中心的正确测定对测量效果的影响以及PSD的定位特性和3D-CCD的响应特性,并由此提出了PSD光强重心定位法和CCD的RGB均衡法,有效地解决了衍射中心确定、峰值饱和、散射连续响应、散射角θ的分辨率等问题,同时结合Shifrin积分变换对测量进行了改进,较好地获得了微粒的连续粒度分布谱图n(D)。