浅谈半导体器件静电损伤及防护措施

本文论述了半导体器件静电损伤及防护措施，阐述了静电放电（ＥＳＤ）失效的敏感电压、静电放电模型、静电对ＣＭＯＳ电路的损伤、提高器件抗静电损伤的方法、无静电工作环境的建立以及包装、储存、运输时防静电的措施。     

静电对光纤接入网设备的危害及防护

阐述静电的成因以及静电放电对光纤接入网设备危害,介绍了光纤接入网设备用的芯片ＰＥＢ２２５４、ＰＥＢ２４６６（ＳＩＥＭＥＮＳ公司生产）,ＭＴ９０７９、ＭＨ８９７９３、Ｌ３０３７（意法－半导体公司）的静电防护原理,对光纤接入网的电气性能和传输参数经受静电放电后冲击的的变化进行了分析。建议对光纤接入网设备（包括ＯＬＴ端和ＯＮＵ端）进行系统的静电防护,对机房的工作台、椅子、地板、人体腕带进行静电接地,强调     

深亚微米低压CMOS IC的ESD保护方法

详述了目前用于亚微米ＣＭＯＳＩＣ的静电放电保护方法,比较了它们各自的特点,并详细阐述了栅耦合ＰＭＯＳ触发／ＮＭＯＳ触发横向可控硅ＥＳＤ保护电路的工作原理。     

静电与静电防护

静电与静电防护赵怀科（电子工业部第４５研究所甘肃平凉７４４０００）１前言电子技术的发展，高分子化学制品的大量应用和生产工艺的现代化，因静电放电（ＥｌｅｃｔｒｏＳｔａｔｉｃＤｉｓｃｈａｎｇ以下简称ＥＳＤ）而产生的设备故障和灾害已屡见不鲜，由于静电的产生...     

MOS集成电路生产过程中防静电的讨论

本文介绍了ＭＯＳ集成电路的静电击穿机理，提出了在ＭＯＳ集成电路生产过程中的一些防静电措施。     

具有低温特性的宽频带P－HEMT MMIC LNA

具有低温特性的宽频带Ｐ－ＨＥＭＴ　ＭＭＩＣ　ＬＮＡ《ＩＥＥＥＴＭＴ＆Ｔ》１９９３年第６—７期报道了使用０．２μｍＴ型栅，ＩｎＧａＡｓＰ－ＨＥＭＴ工艺制作了两个８～１８ＧＨＺ宽带单级ＭＭＩＣ低噪声放大器。其中一个为平衡结构的Ｐ－ＨＥＭＴＭＭＩＣＬＮＡ，...     

静电防护措施在电视机生产中的应用

针对电视机生产过程中静电危害,详细分析静电产生以及静电失效机理,并给出具体的静电防护措施.采取静电接地、穿戴静电防护工作服、使用静电防护台面、地面、工具及周转箱、静电防护包装袋等措施,建立静电防护体系.     

IC卡应用系统的可靠性与安全性

文章介绍了ＥＥＰＲＯＭ存贮器卡、加密ＥＥＰＲＯＭ存贮器卡、ＣＰＵ卡、智能卡、ＩＵ卡发行机、ＩＣ卡读写机、ＩＣ卡可靠性、ＩＣ卡信息安全性的特点，决定因素及其设计。     

GaAs器件及MMIC的可靠性研究进展

介绍了国外ＧａＡｓ微波器件及ＭＭＩＣ的可靠性研究进展情况，给出ＧａＡｓＭＥＳＦＥＴ、ＨＥＭＴ和ＭＭＩＣ的主要失效模式和失效机理以及在典型沟道温度下的平均寿命代表值。     

SEMICON China 2002 Shanghai国际半导体设备及材料展览会圆满落幕

20 0 2年ＳＥＭＩＣＯＮＣｈｉｎａ于 3月 2 6～ 2 7日在上海国际展览中心成功举办 ,这是在我国举办的ＳＥＭＩＣＯＮＣｈｉｎａ有史以来规模最大、展商最多、最具轰动的一次展会 ,许多参加过美、日ＳＥＭＩＣＯＮ展览的人士都深有感触地说 ,这次展会从规模和内容上都与国外的ＳＥＭＩＣＯＮ有些接近了。3月 2 6日 ,2 0 0 2年国际半导体设备及材料展览暨研讨会 (ＳＥＭＩＣＯＮＣｈｉｎａ 2 0 0 2 )在上海国际展览中心隆重开幕 ,ＳＥＭＩ总裁兼首席执行官斯坦迈耶斯先生在致词中指出 :中国半导体工业正在与世界半导体工业一起经历着一场巨变…     

电子计量产品接触式静电放电的接地改良研究

在电子工业中,由于静电会损坏电子元器件、严重影响产品质量的问题尚未得到解决,该文对某电子产品（简称被试系统）进行了静电放电（ESD）抗扰度试验,研究了接触式静电放电模式下系统受ESD干扰的情况。当放电电压低于4.5KV时,ESD对于被试系统基本没有影响;当放电电压大于5KV时,受试设备出现蜂鸣器报警、死机现象。通过改进接地,使其抗压能力提高,并对比分析不同接地措施,对进一步改进静电接地提供参考和依据。     

Investigation of high performance Edge Lifted Capacitors reliability for GaAs and GaN MMIC technology

This paper reports extensive investigations of Edge Lifted Capacitors (ELC) and standard metal–insulator–metal (MIM) capacitors with different refractive index and thickness of Silicon Nitride (Si₃N₄) dielectric films. The wafer-level electrical measurements reveal size dependence of capacitances and breakdown voltages. Physical characterization was performed using Fourier transform infrared spectroscopy (FTIR) to understand intrinsic properties of the studied films and failure-related cross sections were used to predict possible leakage mechanisms. Reliability testing of Human Body Model (HBM) and Machine Model (MM) electrostatic discharge (ESD), time-dependent dielectric breakdown (TDDB), and biased high temperature accelerated stress testing (bHAST) were performed and will be reviewed for GaAs and GaN monolithic microwave integrated circuit (MMIC) applications.     

Novel concept for high level overdrive tolerance of GaAs based FETs

A novel FET concept, using low temperature grown GaAs as surface passivation and buffer layer material, has been developed to tolerate high levels of input overdrive and to improve electrostatic discharge (ESD) resistance. It is shown that high input levels 17 dB beyond the 1 dB compression point, do not lead to the burnout of the device and that, at the same time, the ESD failure voltage can be increased compared to conventional GaAs based MESFETs.     

Bottom-contact organic field-effect transistors based on single-crystalline domains of 6,13-bis(triisopropylsilylethynyl) pentacene prepared by electrostatic spray deposition

Large crystalline domains (a few hundred micrometers in size) of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) were prepared by electrostatic spray deposition (ESD) and used as the active layers of bottom-contact organic field-effect transistors. The TIPS pentacene active layers were directly patterned via a shadow mask in the ESD process. The device, which had a 5-μm-long channel composed of a single-crystalline domain, exhibited a high field-effect mobility of more than 0.1 cm²/V s but resulted in a high threshold voltage of −17 V. The threshold voltage could be lowered to −6.4 V by reducing the thickness of the BC electrodes from 30 to 10 nm; this threshold voltage lowering was probably due to an improvement in the charge injection from the source electrode to the active layer.     

静电损伤及其防护措施

本文提出了轻微静电损伤和严重静电损伤的概念,简述了静电放电模型,指出了提高器件抗静电放电能力的对策。     

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

Ku-Band Power Amplifier MMIC Chipset with On-Chip Active Gate Bias Circuit

We propose a Ku-band driver and high-power amplifier monolithic microwave integrated circuits (MMICs) employing a compensating gate bias circuit using a commercial 0.5 μm GaAs pHEMT technology. The integrated gate bias circuit provides compensation for the threshold voltage and temperature variations as well as independence of the supply voltage variations. A fabricated two-stage Ku-band driver amplifier MMIC exhibits a typical output power of 30.5 dBm and power-added efficiency (PAE) of 37% over a 13.5 GHz to 15.0 GHz frequency band, while a fabricated three-stage Ku-band high-power amplifier MMIC exhibits a maximum saturated output power of 39.25 dBm (8.4 W) and PAE of 22.7% at 14.5 GHz.     

A new ESD protection structure for high-speed GaAs RF ICs

We demonstrate a new electrostatic discharge (ESD) protection structure for high-speed GaAs RF ICs. The structure is composed of small diodes and large transistors using an InGaP heterojunction bipolar transistor (HBT) technology. Its loading effect and its robustness are evaluated experimentally. The impedance of the new structure at OFF state, represented with an equivalent shunt capacitance and an equivalent shunt resistance, are 0.22 pF and 500 /spl Omega/ at 10 GHz. The structure can withstand +2700-V and -2900-V human body model ESD pulses. It can clamp voltage more effectively than the conventional diode-based ESD structure. The new structure can be used to protect 10 Gb/s input/output pins of high-speed RF ICs against ESD.     

静电及其防护

静止的电荷有了接地通路时产生静电放电（ESD），在人类的日常生活中这种现象是不可避免地存在的。集成电路技术的发展使电子产品更加小型化和结构复杂性，更易受ESD的攻击，电子制造商每年都因此造成很大的损失。按照防护ESD的五项原则积极防护是电子制造商降低，生产成本，提高产品质量，赢得用户信誉的必由之路。