用于倒装芯片的晶片凸点制作工艺研究

倒装芯片在电子封装互连中占有越来越多的份额,是一种必然的发展趋势,所以对倒装芯片技术的研究变得非常重要。倒装芯片凸点的形成是其工艺过程的关键。现有的凸点制作方法主要有蒸镀焊料凸点、电镀凸点、微球装配方法、焊料转送、在没有UBM的铅焊盘上做金球凸点、使用金做晶片上的凸点、使用镍一金做晶片的凸点等。每种方法都各有其优缺点,适用于不同的工艺要求。介绍了芯片倒装焊基本的焊球类型、制作方法及各自的特点,总结了凸点制作应注意的问题。     

用于倒装芯片的金球凸点制作技术

倒装芯片中凸点用于实现芯片和基板的电路互连,芯片凸点的制作是倒装芯片技术的关键技术之一.对金球凸点制作进行了介绍.金球凸点直接粘附于芯片上,同时又可具有电路互连的作用,可以完成倒装芯片与基板的电气连接.金球凸点的优势是简单、灵活、便捷、低成本,最大特点是无需凸点下金属层(UBM),可对任意大小的单个芯片进行凸点制作,平整度可达到±4μm.     

GaAs芯片上倒装Si芯片的金凸点高度与键合工艺参数优化

随着射频集成电路向小型化、高集成方向发展，基于金凸点热超声键合的芯片倒装封装因凸点尺寸小、高频性能优越成为主流技术之一。以GaAs芯片上倒装Si芯片的互连金凸点为研究对象，通过有限元仿真方法，分析了温度和剪切力作用下不同高度金凸点的等效应力，得到金凸点的最优高度值。通过正交试验，研究键合工艺参数(压力、保持时间、超声功率、温度)对金凸点高度和键合强度的影响规律。通过可靠性试验，验证了工艺优化后倒装焊结构的可靠性。结果表明：键合工艺参数对凸点高度的影响排序为压力>超声功率>温度>保持时间，对剪切力的影响排序为压力>超声功率>保持时间>温度。     

倒装芯片钉头Au凸点的制作与测试

本文简单回顾了倒装芯片（FC）凸点技术的发展和现状，研究了利用传统的金丝球焊机制作钉头Au凸点（SBB）的工艺，初步完成了在微波GaAs芯片上金凸点的制作，测试了凸点的剪切力和接触电阻，为下一步倒装焊的基础工艺研究打下良好的基础。     

采用热压焊工艺实现金凸点芯片的倒装焊接

金凸点芯片的倒装焊接是一种先进的封装技术.叙述了钉头金凸点硅芯片在高密度薄膜陶瓷基板上的热压倒装焊接工艺方法,通过设定焊接参数达到所期望的最大剪切力,分析研究互连焊点的电性能和焊接缺陷,实现了热压倒装焊工艺的优化.同时,还简要介绍了芯片钉头金凸点的制作工艺.     

芯片上Sn／Pb凸点的制作工艺

随着电子产品对小型、轻量、薄型、高性能的需求越来越迫切，使得倒装芯片技术得到了更加广泛的应用，而凸点的形成正是倒装焊接技术中的关键。本文介绍了用电镀法制作Sn／Pb凸点的基本方法，并对其中的厚胶光刻、UBM层溅射、电镀等关键工艺中应该注意的问题进行了描述。     

倒装再分布技术及应用

随着半导体技术的发展,封装工艺与圆片工艺的联系越来越密切,特别是倒装技术的发展及广泛应用。由CSP到WL-CSP,再到TSV技术,封装技术的发展越来越迅速。倒装技术是发展的关键技术,它包括再分布技术、凸点底层金属（UBM）技术、凸点制备技术、倒扣焊接技术和底部填充技术等。文章介绍了传统芯片通过再分布设计及工艺解决实现倒装工艺,为倒装技术以及新技术的开发和应用提供了良好的途径和广阔的空间。     

IC芯片金属凸点的制作

本文简要报道芯片倒装焊技术中ＩＣ芯片金属凸点的一种制作方法；在芯片铝电极上制作了不同薄膜金属化结构的金、铜凸点并对其物理性能界面作了初步分析。     

金凸点的打球法制作与可靠性考核

本文采用打球法在芯片上制作金凸点，并将凸点倒装焊接在Ti/Ni/Au多层金属化的LTCC基板上。利用扫描电镜观察凸点形貌，X射线透射研究倒装互连状况，并通过接触电阻和剪切强度对凸点倒装焊的可靠性进行了考核。     

倒装芯片互连凸点电迁移的研究进展

电子产品向便携化、小型化、高性能方向发展,促使集成电路的集成度不断提高,体积不断缩小,采用倒装芯片互连的凸点直径和间距进一步减小和凸点中电流密度的进一步提高,由此出现电迁移失效引起的可靠性问题.本文回顾了倒装芯片互连凸点电迁移失效的研究进展,论述了电流聚集和焊料合金成分对凸点电迁移失效的影响,指出了倒装芯片互连凸点电迁移研究亟待解决的问题.     

倒装焊技术及应用

随着集成电路封装密度的提高,传统引线键合技术已经无法满足要求,倒装焊技术的发展能够解决该问题,并且得到了广泛的应用。文章介绍了倒装焊中的4种关键工艺技术,即UBM制备技术、凸点制备方法、倒装和下填充技术。其中凸点制备技术直接决定着倒装焊技术的好坏,为满足不同产品的需求,出现了不同的凸点制备技术,使倒装焊技术具备了好的发展前景。文章对各工艺技术的应用特点进行了阐述,并对倒装焊技术的发展前景进行了展望。     

Low cost bumping by stencil printing: process qualification for 200 μm pitch

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.     

焊球植球凸块工艺的可靠性研究

焊球植球是一种最具潜力的低成本倒装芯片凸块制作工艺.采用焊球植球工艺制作的晶圆级芯片尺寸封装芯片的凸块与芯片表面连接的可靠性问题是此类封装技术研究的重点.为此,参考JEDEC关于电子封装相关标准,建立了检验由焊球植球工艺生产的晶圆级芯片尺寸封装芯片凸块与芯片连接及凸块本身是否可靠的可靠性测试方法与判断标准.由焊球植球工艺生产的晶圆级芯片尺寸封装芯片,分别采用高温存储、热循环和多次回流进行试验,然后利用扫描电子显微镜检查芯片上凸块剖面的凸块下金属层分布和测试凸块推力大小来验证凸块的可靠性.试验数据表明焊球植球工艺生产的晶圆级芯片尺寸封装芯片具有高的封装连接可靠性.     

Bump formation for flip chip and CSP by solder paste printing

Area array packages (flip chip, CSP and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment or are limited by the throughput, minimal pitch and yield the industry is currently searching for new and lower cost bumping approaches. In this paper the experimental work of stencil printing to create solder bumps for flip chip and wafer level CSP (CSP-WL) is described in detail.This paper is divided into two parts. In the first part of the paper a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless Nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented and the limits concerning pitch, reproducibility and bump height will be discussed in detail. The second part of the paper is focused on solder paste printing for wafer-level CSPs. In order to achieve large bumps an optimized printing method will be presented. Additionally advanced stencil design will be shown and the achieved results will be compared with conventional methods.     

倒装芯片热电极键合工艺研究

文章将论述一种无掩模制造细小焊料凸点技术。利用热电极键合工艺将带有凸点的倒装芯片焊到基板上。此项工艺能将间距小至40μm的倒装芯片组装到基板上。文章也论述了间距为40μm、电镀AuSn钎料凸点的倒装芯片组装工艺技术。金属间化合物相的形成对焊点可靠性有重要影响,尤其是对于细小焊点。文中研究了金属间化合物相的形成与增加对可靠性的影响。讨论分析了热循环和湿气等可靠性试验结果。     

Numerical analysis of thermo-mechanical and mobility effects for 28 nm node and beyond: Comparison and design consequences over bumping technologies

Thanks to finite elements simulation and dedicated post-processing routines, this paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over the assembly generations is carried out. In order to do so, models are built for solder flip chip, copper pillar flip chip and micro-copper pillar bumping. Design recommendations for MOSFET placement to include in conception tools are provided, which allow to ensure adherence to product specifications while technologies advance.     

Novel Bumping Material for Solder‐on‐Pad Technology

A novel bumping material, which is composed of a resin and Sn3Ag0.5Cu (SAC305) solder power, has been developed for the maskless solder‐on‐pad technology of the fine‐pitch flip‐chip bonding. The functions of the resin are carrying solder powder and deoxidizing the oxide layer on the solder power for the bumping on the pad on the substrate. At the same time, it was designed to have minimal chemical reactions within the resin so that the cleaning process after the bumping on the pad can be achieved. With this material, the solder bump array was successfully formed with pitch of 150 µm in one direction.     

Reliability investigations of hard core solder bumps using mechanical palladium bumps and SnPb solder

The choice of solder joint metallurgy is a key issue especially for the reliability of flip-chip assemblies. Besides the metallurgical systems already widely used and well understood, new materials are emerging as solderable under bump metallization (UBM). For single chip bumping Pd stud bumps form a solid core under the solder layer. These hard core solder bumps are an adequate solution if single dies are available only and the chosen assembly technology is flip chip soldering. The scope of this paper is to summarize the results from aging of lead/tin solder bumps on palladium. The growth of intermetallic and its impact on the mechanical reliability are investigated.     

形成倒装芯片焊点的铜接线柱焊凸(SBC)法

在倒装芯片应用中生长晶圆焊凸的工艺中对于间距较小(即小于150μm)、具有数个尺寸为150μm的焊凸,倒装前的焊锡涂敷好坏对产品的良率和可靠性起着重要作用。因为,如果涂敷的焊锡体积不均匀,就经不起涂敷过程中为确保涂敷在引线框上焊锡的完整和体积一致性而引入的强制视像系统检查,从而降低产出率。这就是一些组装工艺正设法减少或取消这些限制的原因。另一方面,采用直接熔化焊凸的方法来形成焊点是一种速度较快的工艺,但在保证回流处理后的离板高度方面有缺点,导致在温度和功率循环测试中的表现较差。介绍的采用铜接线柱焊凸(SolderBumponCopperStud;SBC)法解决了这些问题;对于那些需要倒装的组装工艺而言,这是可保障其制造性较佳的解决方案。介绍采用铜接线柱焊凸(SBC)工艺在附着在倒装芯片上的金属基片和焊凸之间形成焊点的新方法,利用铜接线柱焊凸技术再配合晶圆级的焊锡丝印工艺在半导体上预先形成焊凸。这是替代电镀焊凸工艺一种别具成本效益的方法。