The prospect of process-induced charging damage in future thin gate oxides

Gate oxide scaling effect on plasma charging damage is discussed for various IC fabrication processes such as metal etching, contact oxide etching, high current ion implantation, and via contact sputtering. Capacitance distortion, stress-induced leakage current, MOSFET characteristics, and circuit performance are used for evaluating the charging damage. We observed that very thin gate oxides are less susceptible to the charging damage because of their lower rate of interface damage, larger charge-to-breakdown, and less device determined stress voltage in the plasma system. We also discuss the diode protection scheme and design techniques for minimizing the charging damage. Latent damage exists after thermal annealing and can be revealed during the subsequent device operation causing circuit performance degradation. High density plasma etching is a trend of the etching technology as it provides better anisotropy, selectivity, and uniformity. Its effects on oxide charging damage is compared with low-density plasma etching. The resistance to process-induced charging damage of future devices appears to be high. This is counter-intuitive and is a good tiding for the future of IC manufacturing. The emergence of alternative gate dielectric raises questions about charging damage that requires further studies.     

Effects of wafer temperature on plasma charging induced damage toMOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O₂ plasma exposure increases from 145°C to 340°C, the damage measured from charge-to-breakdown (Q_bd) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes     

A model and experiments for thin oxide damage from wafer chargingin magnetron plasmas

A physically based model that has been developed to explain the role of plasma nonuniformity in charge damage to oxides is presented. For a uniform plasma the local conduction currents to the water surface integrate to zero over the RF period, and the surface charging is sufficient to damage oxides. For the case of thin oxides under a gate exposed to a nonuniform magnetron plasma, the gate surface can charge up until the oxide tunneling current balances the difference in the mean local conduction currents from the plasma. It is this oxide current that leads to degradation. The oxide current obtained via SPICE circuit simulations, probe measurements and breakdown measurements shows good agreement with experimental damage data of `antenna' capacitors     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

Modeling oxide thickness dependence of charging damage by plasmaprocessing

Develops a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The current is deduced from capacitance-voltage (CV) curves of metal-oxide-semiconductor (MOS) capacitors after plasma etch. The model predicts the oxide thickness dependence of plasma charging successfully. It is shown that plasma acting on a very thin oxide during processing may be modeled as essentially a current source. Thus the damage will not be greatly exacerbated as oxide thickness is further reduced in the future. Gate oxide breakdown voltage distribution of MOS capacitors after plasma processing can be predicted accurately from that of a control wafer by using a defect-induced breakdown model     

Modeling of oxide breakdown from gate charging during resist ashing

Plasma damage was observed after exposing an antenna capacitor structure to an O₂ plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology     

Nondestructive DCIV method to evaluate plasma charging damage inultrathin gate oxides

Understanding and minimizing plasma charging damage to ultrathin gate oxides became a growing concern during the fabrication of deep submicron MOS devices. Reliable detecting techniques are essential to understand its impact on device reliability. As the gate oxide thickness of MOSTs rapidly scales down, the conventional nondestructive methods such as capacitor C-V and threshold voltage and subthreshold swing of MOSTs are no longer effective for evaluating this damage in gate oxide. In this paper, the newly developed direct-current current-voltage (DCIV) technique is reported as an effective monitor for plasma charging damage in ultrathin oxide. The DCIV measurements for p-MOSTs with both 50- and 37-Å gate oxides clearly show the plasma charging damage region on the wafers and are consistent with the results of charge-to-breakdown measurements. In comparing with charge-to-breakdown measurement and other conventional methods, the DCIV technique hits the advantages of nondestructiveness, high sensitivity and rapid evaluation     

A model for n-well junction effect on gate-charging damage inPMOSFETs

A quantitative model explaining N-well junction effect on gate charging damage in PMOSFETs is presented. This model takes into account the reverse-biased N-well junction leakage, generated both thermally and by photons and its behavior on limiting charging current passing through gate oxide during plasma processing. The modeling results suggest that plasma illumination plays a key role in enabling gate charging damage in PMOSFETs. The model can also apply to reverse-biased source and drain junctions in both P and NMOSFETs during plasma events     

Plasma-induced charging evaluation using SCA and PDM tools

Plasma-induced charging has been characterized using unpatterned oxide wafer charging technique. Charging distributions correlate to gate oxide charging damage with antennae structure. Modification of the process by lowering pressure and increasing gas flow led to a significant decrease of the plasma-induced charging and the gate oxide damage     

超薄栅氧化层等离子体损伤的工艺监测

 随着集成电路向深亚微米、纳米技术发展,等离子体充电对制造工艺造成的影响,尤其对超薄隧道氧化层的损伤越来越显著.本文分析了等离子体工艺损伤机理以及天线效应,设计了带有多晶、孔、金属等层次天线监测结构的电容和器件,并有不同的天线比.设计结构简单、完全工艺兼容,测试结果直观、测量灵敏度高等优点,实现了等离子体损伤芯片级工艺监控.测试分析表明,不同的膜层结构,等离子体损伤程度不同,当天线比大于10³以后,充电损伤变得明显.同时测试也发现了工艺损伤较为严重的环节,为优化制造工艺,提高超薄栅氧化层抗等离子体损伤能力提供了科学的依据.     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

A mechanism of gate oxide deterioration during As+ ionimplantation

The deterioration or catastrophic breakdown of thin gate oxides during ion implantation is studied. The effect of ion beam density, the distribution of the gate oxide deterioration over a wafer, and the effect of photoresist coverage are shown quantitatively by measuring the number of interface states generated in MOS capacitors. It is shown that the four charge sources contribute to the deterioration of gate oxide: the irradiated ion beam, the secondary electrons emitted from the gate electrode, the charges accumulated on the photoresist surface around the gate electrode, and the secondary electrons emitted from a wafer holder. The first three charges accelerate the deterioration of the gate oxide and the last one reduces it. A model of the gate oxide deterioration in ion implantation that is very useful for finding methods of reducing the charging damage is presented     

Oxide thickness dependence of plasma charging damage

Charging damage induced in oxides with thickness ranging from 8.7 to 2.5 nm is investigated. Results of charge-to-breakdown (Q_bd) measurements performed on control devices indicate that the polarity dependence increases with decreasing oxide thickness at both room and elevated temperature (180°C) conditions. As the oxide thickness is thinned down below 3 nm, the Q_bd becomes very sensitive to the stressing current density and temperature. Experimental results show that severe antenna effect would occur during plasma ashing treatment in devices with gate oxides as thin as 2.6 nm. It is concluded that high stressing current level, negative plasma charging, and high process temperature are key factors responsible for the damage.     

Gate oxide leakage due to temperature accelerated degradation under plasma charging conditions

Plasma-induced gate charging and resulting damage to the gate oxide during fabrication of submicron devices becomes a serious yield and reliability concern, especially when oxide thickness and device dimensions shrink to the nanoscale region. In this paper experimental results from plasma damaged submicron MOS transistors, namely low-level gate leakage and degraded charge-to-breakdown characteristics, are analyzed with respect to conditions of electrical stress. It is demonstrated that wafer temperature is a crucial parameter for charging-induced oxide degradation due to plasma processing. Laboratory experiments simulating plasma charging showed that low-level oxide leakage is the result of oxide breakdown after electrical wear-out under low-level injection conditions. High field stress, performed at 150°C, confirmed that elevated temperature during plasma processing strongly accelerates oxide degradation and even at low-level stress leads to the effects observed in plasma damaged devices.     

Plasma damage in thin gate MOS dielectrics and its effect on device characteristics and reliability

Plasma process-induced damage continues to be a great threat and concern in the modern CMOS technologies. This article concentrates on NMOS vs. PMOS device sensitivity to plasma charging originating from the various processing steps. This dependence is studied with respect to the gate oxide thickness, and large antenna devices are used to evaluate device yield, latent damage, and residual effect of charging on device performance and reliability. Specific studies are performed to explore the resistance to the charging damage in CMOS devices with a 50 Å gate oxide grown with various oxidation processes.     

The electrostatic charging damage on the characteristics andreliability of polysilicon thin-film transistors during plasmahydrogenation

In this letter, the impacts of electrostatic charging damage on the characteristics and gate oxide integrity of polysilicon thin-film transistors (TFT's) during plasma hydrogenation were investigated. Hydrogen atoms can passivate trap states in the polysilicon channel, however, plasma processing induced the effect of electrostatic charging damages the gate oxide and the oxide/channel interface. The passivating effect of hydrogen atoms is hence antagonized by the generated interface states. TFT's with different area of antennas were used to study the damages caused by electrostatic field     

FGA effects on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step.     

等离子体工艺引起的MOSFET栅氧化层损伤

在深亚微米 MOS集成电路制造中 ,等离子体工艺已经成为主流工艺。而等离子体工艺引起的栅氧化层损伤也已经成为限制 MOS器件成品率和长期可靠性的一个重要因素。文中主要讨论了等离子体工艺引起的充电损伤、边缘损伤和表面不平坦引起的电子遮蔽效应的主要机理 ,并在此基础上讨论了减小等离子体损伤的有效方法。     

Analysis of thin gate oxide degradation during fabrication ofadvanced CMOS ULSI circuits

The electrical characteristics uniquely associated with the thin gate oxide degradation of the advanced CMOS technology in manufacturing were determined for the first time. They were different from Fowler-Nordheim (F-N) stress, and therefore, cannot be simulated by the F-N stress. The p⁺ thin gate oxides were found to be inherently more susceptible to gate oxide degradation than the n⁺ gate oxides. The p⁺ oxide degradation is caused by a combination of the process-induced defect and plasma charging. The nature of the defect and its formation were identified by electrical and physical analysis. The defect formation was modeled. The p-channel gate oxide degradation will be worse with gate oxide scaling, and may limit the device scaling     

Prediction of plasma charging induced gate oxide damage by plasmacharging probe

The plasma processing induced wafer charging damage is predicted by the newly developed SPORT (Stanford Plasma On-wafer Real Time) charging probe. Such a probe can directly measure the spatial charging voltage built up on a wafer surface as well as the charging current from the plasma. Both antenna dependence of damage and charge fluence through a gate oxide due to charging can be calculated from the intersection between plasma I-V characteristic measured by the probe and intrinsic MOS I-V characteristic. This result agrees well with the real MOS capacitor damage data from O₂ plasma processing. Thus, given a fluence criteria, this methodology gives a means for predicting the minimum antenna ratio for observable damage