Bulk Lateral MEM Resonator on Thin SOI With High $Q$ -Factor

The fabrication, design, and characterization of high-quality factor microelectromechanical (MEM) resonators fabricated on thin-film silicon-on-insulators (SOIs) are addressed in this paper. In particular, we investigate laterally vibrating bulk-mode resonators based on connected parallel beams [parallel beam resonators (PBRs)]. The experimental characteristics of PBRs are compared to disk resonators and rectangular plate resonators. All the reported MEM resonators are fabricated on 1.25-mum SOI substrates by a hard mask and deep reactive-ion etching process, resulting in transduction gaps smaller than 200 nm. Additionally, this fabrication process allows the growth of a thermal silicon dioxide layer on the resonators, which is used to compensate the resonance-frequency dependence on temperature. Quality factors Q, ranging from 20 000 at 32 MHz up to 100 000 at 24.6 MHz, are experimentally demonstrated. The motional resistances R _m are compared for different designs, and values as low as 55 kOmega at 18 V of bias voltage are obtained with the thin SOI substrate. The thermal sensitivity of the resonance frequency is investigated from 200 K to 360 K, showing values of -15 ppm/K for the PBRs, with a possible compensation of 2 ppm/K when using 20 nm of SiO₂.     

An advanced reactive ion etching process for very high aspect-ratio sub-micron wide trenches in silicon

This paper reports on a practical modification of the two-step time-multiplexed plasma etching recipe (also known as the Bosch process) to achieve high aspect-ratio sub-micron wide trenches in silicon. Mixed argon and oxygen plasma depassivation steps are introduced in between the passivation and etching phases to promote the anisotropic removal of the passivation layer at the base of the trench. Argon does not chemically react with polymers and silicon and removes the passivation layer only by physical sputtering. Therefore, it results in a highly anisotropic polymer etching process. This recipe can be easily integrated on conventional ICP equipment and the scalloping on the trench sidewall can potentially be reduced in size to less than 50 nm. To clean up all the passivation residues, a short oxygen plasma step is also added at the end of the cycle that effectively improves the uniformity of the etching profile over various opening sizes. Excellent anisotropy of the inserted argon depassivation step facilitates narrow trenches down to 130 nm wide and gap aspect-ratios as high as 40:1, extending the application of deep reactive ion etching (DRIE) processes into a new broad regime.     

Fabrication of an hermetically packaged silicon resonator on LTCC substrate

The design, fabrication and packaging process of silicon resonators capable of the integration of LSI (Large Scale Integration) have been developed on the basis of packaging technology using an LTCC (Low Temperature Co-fired Ceramic) substrate. The structures of silicon resonators are defined by deep reactive ion etching (DRIE) on a silicon on insulator (SOI) wafer and then transferred onto the LTCC substrate and hermetically sealed by anodic bonding technique. The measured resonant frequency of a micromechanical bulk acoustic mode silicon resonator after packaging at 0.02 Pa is 20.24 MHz with a quality factor of 50,600.     

Study of silicon backside damage in deep reactive ion etching for bonded silicon–glass structures

 For devices of bonded silicon and glass structures fabricated by deep reactive ion etching (DRIE), it is important to avoid damage at the silicon sidewall and backside during through-wafer etching in order to ensure reliability of devices. The silicon damage caused by charge accumulation at the glass surface is inhibited by means of an electrically conducting layer patterned onto the glass and connected with the silicon. In this study, indium tin oxide films were applied in order to identify the positions of silicon damage in the structural layout without destruction of samples. From the results, we report that there exists silicon damage caused by charge accumulation at the silicon islands divided by DRIE and we present important rules for mask layout when utilizing this method. Received: 10 August 2001/Accepted: 24 September 2001 This paper was presented at the Fourth International Workshop on high Aspect Ratio Microstructure Technology HARMST 2001 in June 2001.     

Fabrication of Flexible Transducer Arrays With Through-Wafer Electrical Interconnects Based on Trench Refilling With PDMS

Flexible transducer arrays are desired to wrap around catheter tips for side-looking intravascular ultrasound imaging. We present a technique for constructing flexible capacitive micromachined ultrasonic transducer (CMUT) arrays by forming polymer-filled deep trenches in a silicon substrate. First, we etch deep trenches between the bottom electrodes of CMUT elements on a prime silicon wafer using deep reactive ion etching. Second, we fusion-bond a silicon-on-insulator (SOI) wafer to the prime silicon wafer. Once the silicon handle and buried oxide layers are removed from the back side of the SOI wafer, the remaining thin silicon device layer acts as a movable membrane and top electrode. Third, we fill the deep trenches with polydimethylsiloxane, and thin the wafer down from the back side. The 16 by 16 flexible 2-D arrays presented in this paper have a trench width that varies between 6 and 20 ; the trench depth is 150 ; the membrane thickness is 1.83 ; and the final substrate thickness is 150 . We demonstrate the flexibility of the substrate by wrapping it around a needle tip with a radius of 450 (less than catheter size of 3 French). Measurements in air validate the functionality of the arrays. The 250- by 250- transducer elements have a capacitance of 2.29 to 2.67 pF, and a resonant frequency of 5.0 to 4.3 MHz, for dc bias voltages ranging from 70 to 100 V.     

Single mask fabrication process for movable MEMS devices

The current work reports on the realization of movable micromachining devices using self-aligned single-mask fabrication process. Only dry etching process utilizing inductively coupled plasma reactive ion etching was used to release 3D micro structures from single crystal silicon substrate. No wet etching process is required to release the structures as is the case with silicon on insulator (SOI) wafers. Also the developed process does not require an SOI substrate and accordingly dispensing with the application of a wet etching step, thus yielding uniform structures without stiction. The optimized process was applied to realize thermally actuated microgrippers. The article presents the development of the fabrication process and demonstrates the operation of the fabricated device. The optimized process provides an avenue for low cost fabrication of movable micromachining devices without the use of complicated wet etching steps typically associated with SOI substrates.     

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

High aspect-ratio combined poly and single-crystal silicon (HARPSS)MEMS technology

This paper presents a single-wafer high aspect-ratio micromachining technology capable of simultaneously producing tens to hundreds of micrometers thick electrically isolated poly and single-crystal silicon microstructures. High aspect-ratio polysilicon structures are created by refilling hundreds of micrometers deep trenches with polysilicon deposited over a sacrificial oxide layer. Thick single-crystal silicon structures are released from the substrate through the front side of the wafer by means of a combined directional and isotropic silicon dry etch and are protected on the sides by refilled trenches. This process is capable of producing electrically isolated polysilicon and silicon electrodes as tall as the main body structure with various size capacitive air gaps ranging from submicrometer to tens of micrometers. Using bent-beam strain sensors, residual stress in 80-μm-thick 4-μm-wide trench-refilled vertical polysilicon beams fabricated in this technology has been measured to be virtually zero. 300-μm-long 80-μm-thick polysilicon clamped-clamped beam micromechanical resonators have shown quality factors as high as 85 000 in vacuum. The all-silicon feature of this technology improves long-term stability and temperature sensitivity, while fabrication of large-area vertical pickoff electrodes with submicrometer gap spacing will increase the sensitivity of micro-electromechanical devices by orders of magnitude     

基于BOE硅腐蚀现象的硅纳米线制作

介绍一种硅纳米线制作方法.在SOI顶层硅上制作硅纳米梁,通过离子注入形成pnp结构,利用新发现的没有特殊光照时BOE溶液腐蚀pn结n型区域现象,结合BOE溶液氧化硅腐蚀,实现硅纳米线制作.制作完全采用传统MEMS工艺,具有工艺简单,成本低,可控,可靠性好,可批量制作等优点.利用该方法制作出了厚50 nm,宽100 nm的单晶硅纳米线,制作的纳米线可用于一维纳米结构电学性能研究、谐振器研究等.     

Fabrication of micro-trench structures with high aspect ratio based on DRIE process for MEMS device applications

The micro-trench structures with high aspect ratio based on the single crystal silicon substrate are fabricated via the deep reactive ion etching (DRIE) process at different etching patterns. The relationship between the micro-trench structures and the DRIE etching patterns is investigated by simulating and processing. The micro-trench structures are obtained to meet the requirements of some MEMS devices for special applications. The profile roughness and micro-trench structures are observed by the atomic force-microscope and the field emission scanning electron microscopy. The verticality (V) of micro-trench structures is average 0.19 in the oxygen environment. The micro-trench structures exhibit better verticality, less roughness and better stability than that of no oxygen. The scalloping effects gradually decreased and the profile becomes more and more polished.     

Vertical Mirror Fabrication Combining KOH Etch and DRIE of (110) Silicon

This paper presents fabrication of MEMS-actuated optical-quality vertical mirrors as the key active optical components in a silicon optical bench (SOB) technology. The fabrication process is based on a combination of potassium hydroxide (KOH) etch and deep reactive ion etching (DRIE) of (110) SOI wafers. The process starts by creating optical-quality vertical surfaces by KOH etch, followed by an oxidation step to protect them. The patterned wafer is then etched by DRIE to define actuators. The process is designed to allow the KOH etch and DRIE to be independently optimized without compromising either while at the same time meeting the challenge of lithography on high-aspect-ratio structures. Three variations of the fabrication process are demonstrated, two that use double masking layers and one that uses a silicon masking layer. We demonstrate in-plane scanners and fast translational vertical mirrors fabricated using these processes. In addition, we propose extensions of the fabrication process to account for DRIE aspect-ratio limitations. Mask layouts of key SOB building blocks, including vertical mirrors, beam splitters, and parallel-plate actuators, are also presented.$hfill$ [2008-0146]      

High aspect ratio micromachining (HARM) technologies for microinertial devices

 In this paper, we review work on novel, high aspect processes for microinertial components at the Defence Evaluation and Research Agency (DERA). High aspect components may lead to significant cost-performance improvements in both accelerometers and gyroscopes. We have evaluated 3 low temperature process technologies – silicon on insulator (SOI) HARM, UV electroforming and bulk HARM. Prototype microinertial devices fabricated in these technologies are also presented. The potential of the processes for integration with on-chip CMOS electronics is assessed which may be either as part of a fully integrated MEMS process or as “value-added” post-processing on commercial CMOS wafers. Bonded SOI (BSOI) materials has been specially designed for micromachining applications to give a low stress material that is optimised for a sacrificial release process. Trench isolation is achieved by deep dry etching to the buried dielectric. These trenches may be refilled to allow metallisation to reach isolated components. Structures with aspect ratios of up to 50:1 have been realised using a combination of photolithography, deposition and deep dry etching. CMOS compatibility has been demonstrated. The process is an attractive manufacturing technology. Electroforming of nickel in resist moulds formed using conventional UV photolithography has also been investigated. Some of the early limitations with this technology have been overcome by using a new resist technology, SU8. The process needs to mature further, but remains a promising candidate. Bulk HARM uses deep dry etching of a bulk silicon membrane which is defined using wet etching. Device isolation is difficult and process control complex making this the least attractive of the technologies.     

DRIE based technology for 3D silicon barcodes fabrication

Microworld barcoding has become a promising tool for cell biology. Individual and subpopulation cell tracking is of great interest to evaluate cell behaviour. Nowadays, many micrometer and even nanometer size silicon structures can be fabricated using microelectronics techniques. In this work we report for first time the development of 3D barcodes based on silicon substrate. The proposed silicon micromachining technology based on deep reactive ion etching (DRIE) allows to obtain micrometer-sized cylindrical structures with vertical etch profile that defines a bit = 1 and non-vertical etch profile that defines a bit = 0. Although this technology will allow more than 15 bits representation, only 4-8 bits are necessary for cell labelling. The results of this work show that DRIE has become a versatile technique to produce high aspect 3D biocompatible silicon-based barcodes structures for cell studies.     

几种基于MEMS的纳米梁制作方法研究

特征尺度在纳米量级的梁结构是多种纳机电器件的基本结构.提出了几种基于MEMS技术的纳米梁制作方法,通过利用MEMS技术中材料与工艺的特性实现单晶硅纳米梁的制作.在普通(111)硅片上,利用各向异性湿法腐蚀对(111)面腐蚀速率极低的特性,通过干法与湿法腐蚀相结合制成厚度在100 nm以下的纳米梁.该方法不使用SOI硅片,有效控制了成本.在(100)SOI硅片上,通过氧化减薄的方法得到厚度在100 nm以下的多种纳米梁,由于热氧化的精度高,一致性好,该方法重复性与一致性均较好.在(110)SOI硅片上,利用硅的各向异性腐蚀特性以及(110)硅片的晶向特点,制作宽度在100 nm以下的纳米梁,梁的两个侧面是(111)面.     

Process Development for CMOS-MEMS Sensors With Robust Electrically Isolated Bulk Silicon Microstructures

This paper presents a deep reactive-ion etching (DRIE)-based post-CMOS micromachining process that provides robust electrically isolated single-crystal silicon (SCS) microstructures for integrated inertial sensors. Several process issues arise from previously reported three-axis CMOS microelectromechanical system (MEMS) accelerometers, including sidewall contaminations of SCS microstructures in plasma etch and a severe silicon undercut caused by overheating of suspended microstructures. Solutions to these issues have been found and are discussed in detail in this paper. In particular, a lumped-element model is developed to estimate the temperature rise on suspended microstructures in a silicon DRIE process. Based on the thermal modeling and experiments, a thick photoresist layer has been used as a thermal path to avoid the severe silicon undercut. The sidewall contamination problem is also eliminated using the modified CMOS-MEMS process. A three-axis accelerometer with a low-noise, low-power on-chip amplifier has been successfully fabricated using the new process. Footing effect was observed on the backside of the sensor microstructure, but it has little effect on the structural integrity and sensitivity of the sensor.     

Micromachined flat-walled valveless diffuser pumps

The first valveless diffuser pump fabricated using the latest technology in deep reactive ion etching (DRIE) is presented. The pump was fabricated in a two-mask micromachining process in a silicon wafer polished on both sides, anodically bonded to a glass wafer. Pump chambers and diffuser elements were etched in the silicon wafer using DRIE, while inlet and outlet holes are etched using an anisotropic etch. The DRIE etch resulted in rectangular diffuser cross sections. Results are presented on pumps with different diffuser dimensions in terms of diffuser neck width, length, and angle. The maximum pump pressure is 7.6 m H₂O (74 kPa), and the maximum pump flow is 2.3 ml/min for water     

VHF single crystal silicon capacitive elliptic bulk-mode disk resonators-part II: implementation and characterization

This work, the second of two parts, reports on the implementation and characterization of high-quality factor (Q) side-supported single crystal silicon (SCS) disk resonators. The resonators are fabricated on SOI substrates using a HARPSS-based fabrication process and are 3 to 18 /spl mu/m thick. They consist of a single crystal silicon resonant disk structure and trench-refilled polysilicon drive and sense electrodes. The fabricated resonators have self-aligned, ultra-narrow capacitive gaps in the order of 100 nm. Quality factors of up to 46 000 in 100 mTorr vacuum and 26000 at atmospheric pressure are exhibited by 18 /spl mu/m thick SCS disk resonators of 30 /spl mu/m in diameter, operating in their elliptical bulk-mode at /spl sim/150 MHz. Motional resistance as low as 43.3 k/spl Omega/ was measured for an 18-/spl mu/m-thick resonator with 160 nm capacitive gaps at 149.3 MHz. The measured electrostatic frequency tuning of a 3-/spl mu/m-thick device with 120 nm capacitive gaps shows a tuning slope of -2.6 ppm/V. The temperature coefficient of frequency for this resonator is also measured to be -26 ppm//spl deg/C in the temperature range from 20 to 150/spl deg/C. The measurement results coincide with the electromechanical modeling presented in Part I.     

Integrated polysilicon and DRIE bulk silicon micromachining for anelectrostatic torsional actuator

This paper presents a fabrication process that integrates polysilicon surface micromachining and deep reactive ion etching (DRIE) bulk silicon micromachining. The process takes advantage of the design flexibility of polysilicon surface micromachining and the deep silicon structures possible with DRIE. As a demonstration, a torsional actuator driven by a combdrive moving in the out-of-plane direction, consisting of polysilicon fingers and bulk silicon fingers, has been fabricated. The integrated process allows the combdrive to be integrated with any structure made by polysilicon surface micromachining     

Real-time etch-depth measurements of MEMS devices

An in situ, real-time process control tool was developed for MEMS deep reactive-ion etch (DRIE) fabrication. DRIE processes are used to manufacture high-aspect-ratio silicon structures up to several hundred microns thick, which would be difficult or impossible to produce by other methods. DRIE MEMS technologies promise to deliver new devices with increased performance and functionality at lower cost. A major difficulty with DRIE is the control of etch depth. Our research shows that it is possible to monitor the etch depth of various MEMS structures (holes, pillars, trenches, etc.) through measurement and analysis of the infrared reflectance spectrum. Depths as large as 150 μm have been measured. Excellent correlation is found between the etch depths determined by analysis of these measurements and those measured with an SEM. In addition to etch depth, other parameters such as the photoresist thickness (e.g., mask erosion) can be simultaneously extracted. Based on these results, an infrared-reflectance etch monitor was integrated onto a reactive ion etcher at the Berkeley Sensor and Actuator Center for real-time monitoring and end-point determination. The integrated optical metrology system demonstrated accurate real-time monitoring of the etch depth and photoresist mask erosion     

Ultra light-weight and high-resolution X-ray mirrors using DRIE and X-ray LIGA techniques for space X-ray telescopes

We are developing novel ultra light-weight and high-resolution X-ray micro pore optics for space X-ray telescopes. In our method, curvilinear micro pore structures are firstly fabricated by silicon deep reactive ion etching (DRIE) or X-ray LIGA processes. Secondly, side walls of the micro structures are smoothed by magnetic field assisted finishing and/or hydrogen annealing techniques for high reflectivity mirrors. Thirdly, to focus parallel X-ray lights from astronomical objects, these structures are elastically or plastically bent into a spherical shape. Fourthly, the bent structures are stacked to form a multi-stage X-ray telescope. In this paper, we report on fabrication and X-ray reflection tests of silicon and nickel X-ray mirrors using the DRIE and LIGA processes, respectively. For the first time, X-ray reflections were confirmed on both of the mirrors. Estimated rms roughnesses were 5 nm and 3 nm for the silicon and nickel mirrors, respectively.