A 2.5-V sigma-delta modulator for broadband communicationsapplications

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution ΣΔ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-μm double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply     

A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators

A 0.6-V 2-2 cascaded audio delta-sigma ADC is described. It uses a resistor-based sampling technique which achieves high linearity and low-voltage operation without subjecting the devices to large terminal voltages. A low-distortion feed-forward topology combined with nonlinear local feedback results in enhanced linearity by reducing the sensitivity to opamp distortion, and allows increased input amplitude, resulting in higher SNDR. The modulator achieves 82-dB dynamic range and 81-dB peak SNDR in the A-weighted audio signal bandwidth with an OSR of 64. The total power consumption of the modulator is 1 mW from a 0.6-V supply. The prototype occupies 2.9 mm/sup 2/ using a 0.35-/spl mu/m CMOS technology.     

A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSMdual-standard IF reception

A system-oriented approach for the design of a UMTS/GSM dual-standard ΔΣ modulator is presented to demonstrate the feasibility of achieving intermediate frequency (IF) around 100 MHz, high dynamic range, and low power consumption at the same time. The circuit prototype implements 78 MHz IF for GSM and 138.24 MHz for wideband code division multiple access (WCDMA), which are set to be 3/4 of the analog-to-digital converter sampling rate. A two-path IF sampling and mixing topology with a low-pass ΔΣ modulator, run at half the sampling rate, is used. Implemented in 0.25-μm CMOS, the circuit achieves dynamic range and peak signal-to-noise and distortion ratio for GSM of 86 and 72 dB, respectively. The corresponding values for WCDMA are 54 and 52 dB, respectively. Optimization is performed at all stages of design to minimize power consumption. The complete circuit consumes less than 11.5 mW for GSM and 13.5 mW for WCDMA at 2.5-V supply, of which 8 mW is due to the analog part     

A stereo audio chip using approximate processing for decimation andinterpolation filters

A stereo audio chip uses approximate processing techniques in the digital decimation and interpolation filters to reduce its active power dissipation. One pair of analog-to-digital (A/D) converters and one pair of digital-to-analog (D/A) converters have been integrated in a die area of 10.22 mm² in a 0.5 μm CMOS technology. The total power dissipation of these converters without power management is 200 mW when operated from a 5-V power supply. When the signal is fully active, power reductions of 36% for decimation and 17% for interpolation over fixed-order filters are demonstrated. When the signal is 40 dB below overload, power reductions of 67% for decimation and 44% for interpolation over fixed-order filters are observed. The power reductions are 83.1% for A/D converters, and 82.7% for D/A converters, when the signal is silent for a period of time     

A 12-bit 1-Msample/s capacitor error-averaging pipelined A/Dconverter

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (×2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75-μm CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm², including all digital logic and output buffers     

Framework and Research Methodology of Short-Timescale Pulsed Power Phenomena in High-Voltage and High-Power Converters

Various short-timescale transients exist in power electronic converters, particularly in high-voltage and high-power systems. The timescales of these transients are from nanoseconds to microseconds, including a switching transition of power semiconductor devices, commutating processes, and drive signal transmissions. These transient processes directly affect the performance and reliability of power electronic systems. Therefore, it is necessary to study these short-timescale processes. Based on two high-power prototype power converters, a 6000-V/1250-kW three-level adjustable-speed drive and a 10-kW/600-V dc–dc converter, this paper studies the various abnormal behaviors of the converters that occurred during the operation of these converters. Dead bands and accumulated switching errors are also investigated. A combined microscopic pulsed power and macroscopic control strategy was proposed for the design of power electronic converters. Three new concepts for power electronic converters are introduced and validated in this paper: 1) sneak pulse; 2) energy dead band; and 3) transient commutating topology.      

A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

In this paper, the design of a continuous-time baseband sigma-delta (ΣΔ) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF ΣΔ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF ΣΔ modulator is 0.2 mm² in 0.35-μm CMOS     

Very low-voltage digital-audio ΔΣ modulator with 88-dBdynamic range using local switch bootstrapping

A 1-V 1-mW 14-bit ΔΣ modulator in a standard CMOS 0.35-μm technology is presented. Special attention has been given to device reliability and power consumption in a switched-capacitor implementation. A locally bootstrapped symmetrical switch that avoids gate dielectric overstress is used in order to allow rail-to-rail signal switching. The switch constant overdrive also enhances considerably circuit linearity. Modulator coefficients of a single-loop third-order topology have been optimized for low power. Further reduction in the power consumption is obtained through a modified two-stage opamp. Measurement results show that for an oversampling ratio of 100, the modulator achieves a dynamic range of 88 dB, a peak signal-to-noise ratio of 87 dB and a peak signal-to-noise-plus-distortion ratio of 85 dB in a signal bandwidth of 25 kHz     

A CMOS highly linear channel-select filter for 3G multistandardintegrated wireless receivers

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm² in a 0.5-μm chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54), 89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA     

A low-power triple-mode sigma-delta DAC for reconfigurable(WCDMA/TD-SCDMA/GSM) transmitters

A sigma-delta(Σ△) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio(SDR) system is presented.The conversion frequency,transfer function of the digital filter and theΣ△modulator,word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA,TD-SCDMA and GSM standards.TheΣ△DAC fabricated in SMIC 0.13-μm CMOS process occupies a die area of 0.72 mm~2,while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage.The measured SFDR is 62.8/60.1/ 75.5 dB for WCDMA/TD-SCDMA/GSM mode,respectively.     

A 71-MHz CMOS IF-baseband strip for GSM

An intermediate-frequency (IF) baseband strip for a superheterodyne GSM receiver developed in a 0.25-μm CMOS technology is presented. It contains a 71-MHz IF amplifier, programmable between -20 and +60 dB in 2-dB steps; a quadrature demodulator; and two low-pass output filters for channel selection. Measurements show an overall maximum gain of 89 dB and a noise figure of 3.8 dB. Phase and amplitude mismatches of the demodulator are below 10 and 0.1 dB, respectively. The high linearity required by the blocking and intermodulating signals, which are not completely suppressed by the IF filter, has been achieved using 4.7 mA from the 2,5-V power supply     

Reconfigurable ADCs enable smart radios for 4G wireless connectivity

A reconfigurable ADC based on a 2-2 modified cascaded /spl Sigma//spl Delta/ modulator designed for a GSM/WCDMA/WLAN/WiMAX zero-IF receiver has been presented. Employing the second-order feedforward /spl Sigma//spl Delta/ modulator in a 2-2 modified cascaded configuration, a high linearity over 100 kHz/2 MHz/10 MHz signal bandwidth is achieved. The P-DWA technique is applied in the first feedback 4-b DAC to eliminate the spurious tones associated with the multibit DAC nonlinearity in the WLAN/WiMAX modes.     

The design of sigma-delta modulation analog-to-digital converters

The author examines the practical design criteria for implementing oversampled analog/digital converters based on second-order sigma-delta (ΣΔ) modulation. Behavioral models that include representation of various circuit impairments are established for each of the functional building blocks comprising a second-order Σ2gD modulator. Extensive simulations based on these models are then used to establish the major design criteria for each of the building blocks. As an example, these criteria are applied to the design of a modulator that has been integrated in a 3-μm CMOS technology. An experimental prototype operates from a single 5-V supply, dissipates 12 mW, occupies an area of 0.77 mm², and has achieved a measured dynamic range of 89 dB     

A 80-MHz bandpass ΔΣ modulator for a 100-MHz IFreceiver

A fully differential fourth-order bandpass ΔΣ modulator is presented. The circuit is targeted for a 100-MHz GSM/WCDMA-multimode IF-receiver and operates at a sampling frequency of 80 MHz. It combines frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an intermediate frequency of 100 MHz to a digital intermediate frequency of 20 MHz. The modulator is based on a double-delay single-op amp switched-capacitor (SC) resonator structure which is well suited for low supply voltages. Furthermore, the center frequency of the topology is insensitive to different component nonidealities. The measured peak signal-to-noise ratio is 80 and 42 dB for 270 kHz (GSM) and 3.84-MHz (WCDMA) bandwidths, respectively. The circuit is implemented with a 0.35-μm CMOS technology and consumes 56 mW from a 3.0-V supply     

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time (CT) ΣΔ modulator is presented. Designed in the SMIC mixed-signal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ΣΔ modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dBdynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm~2.     

A multicarrier GMSK modulator with on-chip D/A converter for base stations

A multicarrier Gaussian minimum shift keying (GMSK) modulator with a 14-bit on-chip digital-to-analog (D/A) converter is presented. The design contains four GMSK modulators, which generate GMSK modulated carriers at the user-defined center frequencies. In wireless base stations, the modulated transmit signals are usually combined at the RF frequency after power amplification. The multicarrier modulator combines four GMSK modulated signals in the digital domain, thereby eliminating the need for an antenna microwave combiner. A new digital ramp generator and output power-level controller performs both the burst ramping and the dynamic power control in the digital domain. The maximum dynamic performance is obtained by multiplexing two D/A converters with output sampling switches. The digital multicarrier GMSK modulator is designed to fulfill the derived spectrum and phase-error specifications of the GSM 900/1800/1900 base stations for pico-, micro-, and macrocells. The die area of the chip is 26.8 mm/sup 2/ in 0.35-/spl mu/m CMOS (in BiCMOS) technology. Power consumption is 706 mW at 3.3 V with 52 MHz.     

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.     

Design techniques for high-resolution current-mode sigma-deltamodulators

This paper describes techniques for the design of high-resolution oversampling analog-to-digital converters based on current memories. A key point is the reduction of nonlinearities, in particular those introduced by the current switches. A current-memory cell with very high precision and linearity has been designed and used in an experimental third-order Σ-δ modulator in a 0.8-μm digital CMOS process. A linearity of better than 14 b and a maximum signal-to-noise+distortion ratio (SNDR) of 80 dB has been measured for an oversampling ratio (OSR) of 64     

A 14-bit 80-kHz sigma-delta A/D converter: modeling, design andperformance evaluation

The development is described of a sigma-delta A/D (analog-to-digital) converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range. The analog modulator uses a double-integration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Transconductance amplifiers having a 160-MHz f_t were developed for the integrators. The circuit is implemented in a 1.75-μm 5-V CMOS process. The analog circuitry occupies 2 mm² of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software     

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.